party_bid三种数据结构总结

三种数据结构对比
本文探讨了三种不同的数据结构,包括嵌套对象数组、基于ID的大对象以及分离的多个数组结构。详细分析了各自的优缺点,如存储清晰度、操作简便性和扩展性等。
写完三种数据结构有段时间了,现在说一下我的认识,三种数据结构各有优势,
1.第一种是这样的:

activities = [
{
name: "first activity",
sign_ups:[],
bids:[]
},
{
name: "second activity",
sign_ups: [ {name:"张三",phone:"13600000000"} ,{name:"李四",phone:"13600000000"}]
bids:[ {name:"竞价1", biddings :[] },{name:"竞价2",
biddings : [{name: "张三",
phone:"13600000000",
price: "10"}] }]
}
];

这种数据结构在本地存储,看起来结构比较清晰,就只需存储一个大的对象数组,每个对象由三个属性构成,这三个属性分别存储每个活动的活动名称、活动报名信息以及活动竞价信息。其中竞价信息的存储比较复杂,竞价信息的每个对象又嵌套了一个对象数组。所以对竞价信息的增删改查实现起来相对比较复杂.用到了大量的underscore。
比如要存储竞价短信的内容到本地,要像下面这样实现:
bidding.save_bid_=function(activity,phone,bid){
var bids= _.map(activity.bids, function (bid) {
if (bid.name == localStorage.current_bid) {
var bidder = new bidding(localStorage.current_name, phone, bid)
bid.biddings.push(bidder)
}
return bid
})

2.第二种数据结构是这样的:
activities = {
"0":{ name: "first activity",
sign_ups:[],
bids:[],
biddings:{} },

"1": {
name: "second activity",
sign_ups: [ {name:"张三", phone:"13600000000" }]
bids:["竞价1","竞价2"],
biddings:{
"竞价1":[ {phone:"13600000000", price: "12"},
{phone:"15600000000",price: "10"}]
"竞价2":[ {phone:"13600000000",price: "10"}]
}
}

这种存储结构外层是一个大对象,对象里面还对应存储了每个活动的id,每个活动由四个属性构成,比上一种多出一个专门用于保存竞价的数组。这样很容易在页面上渲染出竞价列表,避免了第一种数据结构的经过复杂的运算才能提取出竞价页面需要显示的数据 。这种数据结构很容易实现对其中数据元素的增删改查,用起来很方便。

3.第三种数据结构是这样的:

activities = [{id:"0", name: "first activity" },{id:"1",
name: "second activity"}]


sign_ups = [{name:"张三",phone:"13600000000",activity_id:"0"},
{name:"李四",phone:"13600000000",activity_id:"0"},
{name:"王五",phone:"15600000000",activity_id:"0"}
]
bids = [{name: "竞价1",activity_id:"0",biddings[]},
{name: "竞价1",activity_id:"1",biddings[
{phone:"13600000000", price: "12"},
{phone:"15600000000",price: "10"}]}]

这种数据结构共存了三个数组,每个数组各司其职 ,activities[]用于存储所有的活动名并且为每个活动加上惟一的标识id;sign_ups[]用于存储所有的活动报名信息并给每一条报名信息提供相应的活动id,bids[]用于存放所有的竞价信息,并表明所属的活动以及所属的竞价,相对于以上两种来说,代码上的实现显得更为简单。另外由于本地存储空间的容量限制,可以将三个数组分别存储于三个存储空间,所以这种数据结构的扩展性高于前两种。

另外,对测试的书写形式有了进一步的认识,在测试的代码结构有了一定的了解,对以后的测试编写很有帮助。
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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 4.2 // \ \ Application : MIG // / / Filename : mig_7series_0.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Wed Feb 01 2012 // \___\/\___\ // // Device : 7 Series // Design Name : DDR3 SDRAM // Purpose : // Wrapper module for the user design top level file. This module can be // instantiated in the system and interconnect as shown in example design // (example_top module). // Revision History : //***************************************************************************** //`define SKIP_CALIB `timescale 1ps/1ps module mig_7series_0 ( // Inouts inout [15:0] ddr3_dq, inout [1:0] ddr3_dqs_n, inout [1:0] ddr3_dqs_p, // Outputs output [14:0] ddr3_addr, output [2:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [0:0] ddr3_ck_p, output [0:0] ddr3_ck_n, output [0:0] ddr3_cke, output [0:0] ddr3_cs_n, output [1:0] ddr3_dm, output [0:0] ddr3_odt, // Inputs // Differential system clocks input sys_clk_p, input sys_clk_n, // user interface signals output ui_clk, output ui_clk_sync_rst, output mmcm_locked, input aresetn, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // Slave Interface Write Address Ports input [3:0] s_axi_awid, input [28:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input [0:0] s_axi_awlock, input [3:0] s_axi_awcache, input [2:0] s_axi_awprot, input [3:0] s_axi_awqos, input s_axi_awvalid, output s_axi_awready, // Slave Interface Write Data Ports input [127:0] s_axi_wdata, input [15:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, // Slave Interface Write Response Ports input s_axi_bready, output [3:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, // Slave Interface Read Address Ports input [3:0] s_axi_arid, input [28:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input [0:0] s_axi_arlock, input [3:0] s_axi_arcache, input [2:0] s_axi_arprot, input [3:0] s_axi_arqos, input s_axi_arvalid, output s_axi_arready, // Slave Interface Read Data Ports input s_axi_rready, output [3:0] s_axi_rid, output [127:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, output init_calib_complete, output [11:0] device_temp, `ifdef SKIP_CALIB output calib_tap_req, input calib_tap_load, input [6:0] calib_tap_addr, input [7:0] calib_tap_val, input calib_tap_load_done, `endif input sys_rst ); // Start of IP top instance mig_7series_0_mig u_mig_7series_0_mig ( // Memory interface ports .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), .ddr3_ck_n (ddr3_ck_n), .ddr3_ck_p (ddr3_ck_p), .ddr3_cke (ddr3_cke), .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), .ddr3_dq (ddr3_dq), .ddr3_dqs_n (ddr3_dqs_n), .ddr3_dqs_p (ddr3_dqs_p), .init_calib_complete (init_calib_complete), .ddr3_cs_n (ddr3_cs_n), .ddr3_dm (ddr3_dm), .ddr3_odt (ddr3_odt), // Application interface ports .ui_clk (ui_clk), .ui_clk_sync_rst (ui_clk_sync_rst), .mmcm_locked (mmcm_locked), .aresetn (aresetn), .app_sr_req (app_sr_req), .app_ref_req (app_ref_req), .app_zq_req (app_zq_req), .app_sr_active (app_sr_active), .app_ref_ack (app_ref_ack), .app_zq_ack (app_zq_ack), // Slave Interface Write Address Ports .s_axi_awid (s_axi_awid), .s_axi_awaddr (s_axi_awaddr), .s_axi_awlen (s_axi_awlen), .s_axi_awsize (s_axi_awsize), .s_axi_awburst (s_axi_awburst), .s_axi_awlock (s_axi_awlock), .s_axi_awcache (s_axi_awcache), .s_axi_awprot (s_axi_awprot), .s_axi_awqos (s_axi_awqos), .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), // Slave Interface Write Data Ports .s_axi_wdata (s_axi_wdata), .s_axi_wstrb (s_axi_wstrb), .s_axi_wlast (s_axi_wlast), .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), // Slave Interface Write Response Ports .s_axi_bid (s_axi_bid), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), // Slave Interface Read Address Ports .s_axi_arid (s_axi_arid), .s_axi_araddr (s_axi_araddr), .s_axi_arlen (s_axi_arlen), .s_axi_arsize (s_axi_arsize), .s_axi_arburst (s_axi_arburst), .s_axi_arlock (s_axi_arlock), .s_axi_arcache (s_axi_arcache), .s_axi_arprot (s_axi_arprot), .s_axi_arqos (s_axi_arqos), .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), // Slave Interface Read Data Ports .s_axi_rid (s_axi_rid), .s_axi_rdata (s_axi_rdata), .s_axi_rresp (s_axi_rresp), .s_axi_rlast (s_axi_rlast), .s_axi_rvalid (s_axi_rvalid), .s_axi_rready (s_axi_rready), // System Clock Ports .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .device_temp (device_temp), `ifdef SKIP_CALIB .calib_tap_req (calib_tap_req), .calib_tap_load (calib_tap_load), .calib_tap_addr (calib_tap_addr), .calib_tap_val (calib_tap_val), .calib_tap_load_done (calib_tap_load_done), `endif .sys_rst (sys_rst) ); // End of IP top instance endmodule 这是mig的例化模板
11-11
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