party_bid三种数据结构

本文详细探讨了三种不同的数据结构在处理party_bid业务需求时的优势和劣势,对比了它们在存储竞价信息、提取关键数据以及存取过程方面的表现。重点介绍了如何通过编程实现数据结构的创建和更新,旨在帮助开发者选择最适合特定场景的数据组织方式。
写完party_bid三种数据结构有几天了,这是第一次接触测试代码,对测试驱动开发有了一点理解,今天来总结一下我对这三种数据结构优势劣势的认识:
1.第一种数据结构:

activities = [
{
name: "first activity",
sign_ups:[],
bids:[]
},
{
name: "second activity",
sign_ups: [
{
name:"仝键",
phone:"13600000000"
}
],
bids:[
{
name:"竞价1",
biddings : [
{
name: "仝键",
phone:"13600000000",
price: "12"
}
]
}
]
}
]

这种数据结构比较清晰,整个数据结构最外层只有一个对象数组,每个对象中包含三个属性分别是每个活动的活动名称,活动的报名信息及竞价信息,其中竞价信息的数组中又嵌套了对象,每个对象由竞价名和竞价名对应的竞价信息组成,所以这部分比较复杂;虽然这种数据结构整体比较清晰但是存取起来很复杂。
这种数据结构要想存储竞价信息,可以通过一下代码实现:

bid.create_new_bid = function (activity_name) {
var activities = JSON.parse(localStorage.getItem("activities")) || [];
var bid = _.map(activities, function (list) {
if (list.name == activity_name) {
var counter = list.bids.length + 1;
var name = "竞价" + counter;
list.bids.push({"name": name, "biddings": []});
}
return list;
})
localStorage.setItem("activities", JSON.stringify(bid))
}

2.第二种数据结构:

activities = {
"0":{
name: "first activity",
sign_ups:[],
bids:[],
biddings:{}
},
"1": {
name: "second activity",
sign_ups: [
{
name:"仝键",
phone:"13600000000"
}
],
bids:["竞价1","竞价2"],
biddings:{
"竞价1":[
{
phone:"13600000000",
price: "12"
}
],
"竞价2": [
{
phone:"13600000000",
price: "10"
}
]
}
}
}

这种数据结构也比较清晰,但是与第一种数据结构有所不同的是整个存储结构最外层是一个大对象,这个对象里存储着每个活动的id号,每个id下存储着活动名称,报名信息,竞价名称及竞价信息四个属性,与第一种数据结构相比多出了一个用来存储竞价名称的数组,这样就更容易提取出竞价页面需要显示的数据,避免了复杂的存取过程,相比之下存取更简单。
这种数据结构要想存储竞价信息,可以通过一下代码实现,(相比第一种更为简单):

bidding.create_new_bid = function (activity_name) {
var activities = JSON.parse(localStorage.activities);
var counter = activities[activity_name].bids.length + 1;
var name = "竞价" + counter;
activities[activity_name].bids.push({"name": name})
activities[activity_name].biddings[name] = [];
localStorage.setItem("activities", JSON.stringify(activities))
}

3.第三种数据结构:

activities = [
{
id:"0",
name: "first activity"
},
{
id:"1",
name: "second activity"
}
];

sign_ups = [
{
name:"仝键",
phone:"13600000000",
activity_id:"0"
},{
name:"仝",
phone:"13600000000",
activity_id:"1"
}
]
bids = [
{
name: "竞价1",
activity_id:"0",
biddings:[
{
phone:"13600000000",
price: "9"
}
]
}
]

这种数据结构没有前两种清晰,包括了三个数组,扩展性优于前两种,并且代码上的实现更为简单。每个数组都存储着各自相关的信息,activities[]存储每个活动独有的id标记,sign_ups[]存储活动的报名信息并通过id标记来区分报名信息,bids[]存储竞价信息,并表明所属的活动以及所属的竞价。
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. 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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 4.2 // \ \ Application : MIG // / / Filename : mig_7series_0.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Wed Feb 01 2012 // \___\/\___\ // // Device : 7 Series // Design Name : DDR3 SDRAM // Purpose : // Wrapper module for the user design top level file. This module can be // instantiated in the system and interconnect as shown in example design // (example_top module). // Revision History : //***************************************************************************** //`define SKIP_CALIB `timescale 1ps/1ps module mig_7series_0 ( // Inouts inout [15:0] ddr3_dq, inout [1:0] ddr3_dqs_n, inout [1:0] ddr3_dqs_p, // Outputs output [14:0] ddr3_addr, output [2:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [0:0] ddr3_ck_p, output [0:0] ddr3_ck_n, output [0:0] ddr3_cke, output [0:0] ddr3_cs_n, output [1:0] ddr3_dm, output [0:0] ddr3_odt, // Inputs // Differential system clocks input sys_clk_p, input sys_clk_n, // user interface signals output ui_clk, output ui_clk_sync_rst, output mmcm_locked, input aresetn, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // Slave Interface Write Address Ports input [3:0] s_axi_awid, input [28:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input [0:0] s_axi_awlock, input [3:0] s_axi_awcache, input [2:0] s_axi_awprot, input [3:0] s_axi_awqos, input s_axi_awvalid, output s_axi_awready, // Slave Interface Write Data Ports input [127:0] s_axi_wdata, input [15:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, // Slave Interface Write Response Ports input s_axi_bready, output [3:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, // Slave Interface Read Address Ports input [3:0] s_axi_arid, input [28:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input [0:0] s_axi_arlock, input [3:0] s_axi_arcache, input [2:0] s_axi_arprot, input [3:0] s_axi_arqos, input s_axi_arvalid, output s_axi_arready, // Slave Interface Read Data Ports input s_axi_rready, output [3:0] s_axi_rid, output [127:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, output init_calib_complete, output [11:0] device_temp, `ifdef SKIP_CALIB output calib_tap_req, input calib_tap_load, input [6:0] calib_tap_addr, input [7:0] calib_tap_val, input calib_tap_load_done, `endif input sys_rst ); // Start of IP top instance mig_7series_0_mig u_mig_7series_0_mig ( // Memory interface ports .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), .ddr3_ck_n (ddr3_ck_n), .ddr3_ck_p (ddr3_ck_p), .ddr3_cke (ddr3_cke), .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), .ddr3_dq (ddr3_dq), .ddr3_dqs_n (ddr3_dqs_n), .ddr3_dqs_p (ddr3_dqs_p), .init_calib_complete (init_calib_complete), .ddr3_cs_n (ddr3_cs_n), .ddr3_dm (ddr3_dm), .ddr3_odt (ddr3_odt), // Application interface ports .ui_clk (ui_clk), .ui_clk_sync_rst (ui_clk_sync_rst), .mmcm_locked (mmcm_locked), .aresetn (aresetn), .app_sr_req (app_sr_req), .app_ref_req (app_ref_req), .app_zq_req (app_zq_req), .app_sr_active (app_sr_active), .app_ref_ack (app_ref_ack), .app_zq_ack (app_zq_ack), // Slave Interface Write Address Ports .s_axi_awid (s_axi_awid), .s_axi_awaddr (s_axi_awaddr), .s_axi_awlen (s_axi_awlen), .s_axi_awsize (s_axi_awsize), .s_axi_awburst (s_axi_awburst), .s_axi_awlock (s_axi_awlock), .s_axi_awcache (s_axi_awcache), .s_axi_awprot (s_axi_awprot), .s_axi_awqos (s_axi_awqos), .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), // Slave Interface Write Data Ports .s_axi_wdata (s_axi_wdata), .s_axi_wstrb (s_axi_wstrb), .s_axi_wlast (s_axi_wlast), .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), // Slave Interface Write Response Ports .s_axi_bid (s_axi_bid), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), // Slave Interface Read Address Ports .s_axi_arid (s_axi_arid), .s_axi_araddr (s_axi_araddr), .s_axi_arlen (s_axi_arlen), .s_axi_arsize (s_axi_arsize), .s_axi_arburst (s_axi_arburst), .s_axi_arlock (s_axi_arlock), .s_axi_arcache (s_axi_arcache), .s_axi_arprot (s_axi_arprot), .s_axi_arqos (s_axi_arqos), .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), // Slave Interface Read Data Ports .s_axi_rid (s_axi_rid), .s_axi_rdata (s_axi_rdata), .s_axi_rresp (s_axi_rresp), .s_axi_rlast (s_axi_rlast), .s_axi_rvalid (s_axi_rvalid), .s_axi_rready (s_axi_rready), // System Clock Ports .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .device_temp (device_temp), `ifdef SKIP_CALIB .calib_tap_req (calib_tap_req), .calib_tap_load (calib_tap_load), .calib_tap_addr (calib_tap_addr), .calib_tap_val (calib_tap_val), .calib_tap_load_done (calib_tap_load_done), `endif .sys_rst (sys_rst) ); // End of IP top instance endmodule 这是mig的例化模板
11-11
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