本文介绍了如何在两个异步时钟域之间约束特定路径。使用`set_clock_association`命令配合`-async_to_async`选项可以保留SI分析并进行定时分析。之后，可以利用`set_max_delay`命令来指定所需路径的最大延迟。为了防止报告其他路径，可以为剩余路径设置无限最大延迟。
Description
Question:
How can I constrain a few paths between two asynchronous clock domains?
Answer:
Specifying asynchronous relationship between clocks does two things:
- Sets a false_path exception internally for all the paths between the two clock domains
- Infinite arrival_window is used for SI analysis between the nets corresponding from these domains
The internal false_path exception suppresses the default timing analysis and as false_path has highest priority over all the other exceptions, you can't use set_max_delay to constrain the required paths directly.
The solution is to use the switch -allow_paths while specifying the asynchronous relationship. The switch enables the timing analysis between the paths and preserves SI analysis using an infinite arrival window:
pt_shell
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