我所知道的EC====>IDLE &RESET MODE

本文介绍了EC在BIOS更新过程中扮演的角色,包括IDLE模式和RESET模式的使用场景及其实现过程。IDLE模式主要用于BIOS更新NVRAM区域,而RESET模式则用于刷新BIOS。

我所知道的EC====>IDLE & RESET MODE

 

  1. What’s this?

 

   IDLE & RESETEC的两种工作模式,从字面上看IDLE是空闲的意思而RESET则是复位的意思。他们的使用场景各有不同,IDLE主要是用在BIOS更新NVRAM区域,RESET则是用于flash bios的时候。

 

  1. Why & How

Ø      IDLE Mode

BIOSpost过程中会多次进入IDLE Mode,用于保存一些系统设置,以及保存硬件资源供OS获取。那么这些操作跟EC有什么关系呢?原因是NVRAM包含多个区域,有些部分保存在CMOS之中,可是还有很多信息保存在ROM之中,很多时候BIOSEC code 放在一颗ROM之中,那么这时就非常有必要让EC进入IDLE mode。另外BIOS在更新NVRAM的时候,EC端有可能通过KBSMI/KBSCI以及其他一些接在SB上的pin影响到BIOS(这部分纯属猜测J)。IDLE Mode的实现过程是这样的,当BIOS需要跟新NVRAM时,它发命令告诉ECEC收到命令后关掉LPC(假设EC通过LPC连到SB)的write protection,然后EC保存寄存器的内容,关掉中断只保留一个唤醒源(如EC host command wake up),然后回给BIOS “FA”表示进入IDLE,最后一步停掉8051 clock真正进入IDLE。那么为什么要先回”FA”然后再进IDLE,因为进IDLE以后8051 clock停掉了,EC无法跑code了,这样也造成了一个隐患,有时BIOS收到”FA”就开始更新NVRAM了,可是这时EC还没有进入IDLE modeEC的速度和host没法比)那就惨了,系统可能会hang住,我就遇到过这样的bugL,所以BIOS收到”FA”最好delay一段时间。BIOS更新完成后给66port随便送个commandEC就会从IDLE恢复了。

 

Ø      RESET MODE

flash bios的时候,BIOS会发命令让EC进入RESET mode,只所以称之为RESET,是由于ROM更新以后EC要重新开始跑code,所以有一个RESET的动作。RESET mode的做法是EC停掉sustain fetch,也就是说EC不去预取指令了,需要跑一条指令才会去抓一条。然后EC关掉所有中断并关掉Write Protection,让风扇全速转(因为刷BIOS时能耗比较大温度会很高),回给BIOS ”FA”,接下来EC就会进入死循环。一旦BIOS检测到flash已经完成,BIOS将会通过back door修改EC register 8051 reset pc复位到0地址处,这时EC就会重新加载新的code

 

 

     以上就是IDLE &RESET Mode的完整过程。

 

       

Peter

这是设备树的信息,请结合进行分析 / { cpus { #address-cells = <0x01>; #size-cells = <0x00>; cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80000>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80100>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80200>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x80300>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@4 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90000>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@5 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90100>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@6 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90200>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; cpu@7 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x90300>; enable-method = "spin-table"; cpu-release-addr = <0x00 0xfff8>; }; }; cpu_extra_info { compatible = "cpu_info,extra_info"; cpu_desc = "1230"; cpu_num = <0x08>; cpu_version = "HI1230V100"; }; interrupt-controller@c1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <0x03>; #address-cells = <0x02>; #size-cells = <0x02>; ranges; interrupt-controller; #redistributor-regions = <0x01>; redistributor-stride = <0x00 0x40000>; reg = <0x00 0xc1000000 0x00 0x10000 0x00 0xc1100000 0x00 0x200000>; phandle = <0x01>; }; timer { compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0x01 0x07 0x08>; }; peripherals { compatible = "simple-bus"; #address-cells = <0x01>; #size-cells = <0x01>; ranges = <0x00 0x00 0x00 0xffffffff>; refclk200mhz { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0xbebc200>; clock-output-names = "refclk200mhz"; phandle = <0x02>; }; uart@fa510000 { compatible = "snps,dw-apb-uart"; #address-cells = <0x01>; #size-cells = <0x00>; reg = <0xfa510000 0x10000>; interrupts = <0x00 0x67 0x04>; clocks = <0x02>; clock-names = "apb_pclk"; reg-shift = <0x02>; }; watchdog: wtd@fa0a290c { compatible = "analog,adm706"; reg = <0xfa0a290c 0x1>; /* 寄存器喂狗*/ status = "okay"; }; sdhci@fb400000 { compatible = "hisilicon,sdhci-hi309a"; reg = <0xfb400000 0x10000>; #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x61 0x04>; bus-width = <0x04>; max-frequency = <0x5f5e100>; mmc-hs200-1_8v; non-removable; wp-inverted; use-pio; sdc_ctrl_reg = <0xfa053238>; hc-type = <0x00>; mmcard@0 { reg = <0x00>; compatible = "mmc-card"; broken-hpi; }; }; uart@fa520000 { compatible = "snps,dw-apb-uart"; #address-cells = <0x01>; #size-cells = <0x00>; reg = <0xfa520000 0x10000>; interrupts = <0x00 0x68 0x04>; current-speed = <0x2580>; clocks = <0x02>; clock-names = "apb_pclk"; reg-shift = <0x02>; }; }; subctrl { compatible = "hisi_subctrl"; #address-cells = <0x02>; #size-cells = <0x02>; peri_subctrl@0 { reg = <0x00 0xfa050000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "peri_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x05>; }; poe_subctrl@0 { reg = <0x00 0xc0050000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "poe_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x03>; }; sppe_subctrl@0 { reg = <0x00 0xd8850000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "sppe0_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x09>; }; eth_subctrl@0 { reg = <0x00 0xf5050000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "eth_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x04>; }; sysctrl@0 { reg = <0x00 0xfa0a0000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "sys_ctrl"; #clock-cells = <0x01>; #reset-cells = <0x01>; }; hilinkmux_subctrl@0 { reg = <0x00 0xf50c0000 0x00 0x10000>; reg-name = "subctrl"; subctrl-name = "hilinkmux_sub"; #clock-cells = <0x01>; #reset-cells = <0x01>; }; }; poe { compatible = "hisi, poe-v100"; #address-cells = <0x02>; #size-cells = <0x02>; interrupts = <0x00 0x1a5 0x01 0x00 0x1a6 0x01 0x00 0x1a7 0x01 0x00 0x1a8 0x01 0x00 0x1a9 0x01 0x00 0x1aa 0x01 0x00 0x1ab 0x01 0x00 0x1ac 0x01 0x00 0x1ad 0x01 0x00 0x1ae 0x01 0x00 0x1af 0x01 0x00 0x1b0 0x01 0x00 0x1b1 0x01 0x00 0x1b2 0x01 0x00 0x1b3 0x01 0x00 0x1b4 0x01>; poe_int_index = <0x00>; status = "okay"; vf_num = <0x01>; pf { reg = <0x00 0xc7000000 0x00 0x800000>; poe_acc_pf = <0x00 0xc7000000 0x00 0x800000>; poe_acc_add_pkt_baddr_pf = <0x00 0xc0480000 0x00 0x10000>; poe_forward_tm_baddr_pf = <0x00 0xf4880100 0x00 0x10000>; poe_send_tm_baddr_pf = <0x00 0xf48800c0 0x00 0x10000>; poe_add_tm_credit_baddr_pf = <0x00 0xf4006000 0x00 0x10000>; poe_send_bmu_baddr_pf = <0x00 0xc03851e0 0x00 0x10000>; poe_send_sppe_credit_baddr_pf = <0x00 0xd000f0d0 0x00 0x10000>; poe_send_sppe_emio_credit_baddr_pf = <0x00 0xd000f0c0 0x00 0x10000>; poe_msg_sppe_baddr_pf = <0x00 0xd0040100 0x00 0x10000>; poe_send_sec_credit_baddr_pf = <0x00 0xfd805604 0x00 0x10000>; poe_msg_sec_baddr_pf = <0x00 0xfd805840 0x00 0x10000>; lcpu_mode = <0x02>; clk_poe_group0 { clk_group_id = <0x00>; clocks = <0x03 0x00>; clock-names = "CLK_POE_CLK0"; at_user = <0x01>; }; rst_poe_group0 { rst_group_id = <0x00>; resets = <0x03 0x00>; reset-names = "RST_POE_RST0"; at_user = <0x01>; }; }; vf0 { reg = <0x00 0xc7800000 0x00 0x100000 0x00 0xcc000000 0x00 0x800000 0x00 0xc0480000 0x00 0x20000>; reg-names = "reg\0poe_grp_vf\0poe_acc_vf"; cpu_get_grp_pbase = <0x00 0xcc000000 0x00 0x800000>; ovfl_addr = <0x04 0xC0100000 0x00 0x400000>; // 4M reserv vqi_def_map_mode = <0x01>; vf_endian = <0x00>; vcpu_num = <0x10>; vcpu_grp_num = <0x10>; vacc_grp_num = <0x12>; interrupt-names = "irq_poe0_group12\0irq_poe0_group13"; }; }; ppe { compatible = "hisi, ppe-v110"; #address-cells = <0x02>; #size-cells = <0x02>; bd_version = <0x00>; status = "okay"; pf { reg = <0x00 0xf0000000 0x00 0x800000>; vf_num = <0x01>; deft_fw_mod = <0x01>; deft_fw_tnl = <0x00>; /* enable rss use for kernel path enable_rss = <0x01>; mam_pool_num_vf0 = <0x04>; mam_pool_depth_vf0 = <0x100 0x100 0x100 0x100>; */ /* enable rss use for dpdk path enable_rss = <0x01>; mam_pool_num_vf0 = <0x08>; mam_pool_depth_vf0 = <512 0x40 0x40 0x40 0x40 0x40 0x40 0x40>; */ enable_rss = <0x00>; // 0 means disable rss mam_pool_num_vf0 = <0x10>; mam_pool_depth_vf0 = <0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40>; ppe_cport_alloc_num = <0x1a>; smmu_type = <0x00>; fw_grp_num_per_vf = <0x10>; bd_endian = <0x00>; fw1_flow_res_range = <0x00 0x00>; fw1_flow_bit_mode = <0x01>; fw2_flow_res_range = <0x01 0x01>; fw2_flow_bit_mode = <0x01>; ig1_flow_res_range = <0x00 0x00>; ig1_flow_bit_mode = <0x02>; ig2_flow_res_range = <0x01 0x01>; ig2_flow_bit_mode = <0x02>; eg1_flow_res_range = <0x02 0x02>; eg1_flow_bit_mode = <0x02>; clk_ppe_group_0 { clk_group_id = <0x00>; clocks = <0x04 0x01>; clock-names = "CLK_PPE_CLK0"; at_user = <0x01>; }; rst_ppe_group_0 { rst_group_id = <0x00>; resets = <0x04 0x01 0x04 0x02>; reset-names = "RST_PPE_RST0\0RST_PPE_RST1"; at_user = <0x01>; }; }; vf0 { reg = <0x00 0xf0800000 0x00 0x100000>; buf_endian_mode = <0x00>; buf_adp_en = <0x00>; buf_big_adp_en = <0x00>; }; }; sub_ctrl_c@60000000 { compatible = "hisilicon,peri-subctrl\0syscon"; reg = <0x00 0xfa050000 0x00 0x10000>; phandle = <0x07>; }; mac_serdes { compatible = "mac_serdes"; reg = <0x00 0xf1000000 0x00 0x800000>; chip_id = <0x00>; pf_id = <0x00>; mag_mac_msi_region = <0x00 0x1a>; interrupts = <0x00 0x142 0x01 0x00 0x143 0x01 0x00 0x144 0x01 0x00 0x145 0x01 0x00 0x146 0x01 0x00 0x147 0x01 0x00 0x148 0x01 0x00 0x149 0x01 0x00 0x14a 0x01 0x00 0x14b 0x01 0x00 0x14c 0x01 0x00 0x14d 0x01 0x00 0x14e 0x01 0x00 0x14f 0x01 0x00 0x150 0x01 0x00 0x151 0x01 0x00 0x152 0x01 0x00 0x153 0x01 0x00 0x154 0x01 0x00 0x155 0x01 0x00 0x156 0x01 0x00 0x157 0x01 0x00 0x158 0x01 0x00 0x159 0x01 0x00 0x15a 0x01 0x00 0x15b 0x01>; interrupt-names = "irq_mag_mac0_port0\0irq_mag_mac0_port1\0irq_mag_mac0_port2\0irq_mag_mac0_port3\0irq_mag_mac0_port4\0irq_mag_mac0_port5\0irq_mag_mac0_port6\0irq_mag_mac0_port7\0irq_mag_mac0_port8\0irq_mag_mac0_port9\0irq_mag_mac0_port10\0irq_mag_mac0_port11\0irq_mag_mac0_port12\0irq_mag_mac0_port13\0irq_mag_mac0_port14\0irq_mag_mac0_port15\0irq_mag_mac0_port16\0irq_mag_mac0_port17\0irq_mag_mac0_port18\0irq_mag_mac0_port19\0irq_mag_mac0_port20\0irq_mag_mac0_port21\0irq_mag_mac0_port22\0irq_mag_mac0_port23\0irq_mag_mac0_port24\0irq_mag_mac0_port25"; status = "okay"; clk_mag_group0 { clk_group_id = <0x00>; clocks = <0x04 0x03 0x04 0x04 0x04 0x05 0x04 0x06 0x04 0x07>; clock-names = "CLK_MAG_CLK0\0CLK_MAG_CLK1\0CLK_MAG_CLK2\0CLK_MAG_CLK3\0CLK_MAG_CLK4"; at_user = <0x01>; }; rst_mag_group { rst_group_id = <0x00>; resets = <0x04 0x08 0x04 0x09 0x04 0x0a 0x04 0x0b>; reset-names = "RST_MAG_RST0\0RST_MAG_RST1\0RST_MAG_RST2\0RST_MAG_RST3"; at_user = <0x01>; }; rst_mag_macv110_x4_t_group { rst_group_id = <0x01>; resets = <0x04 0x0c 0x04 0x0d 0x04 0x0e 0x04 0x0f 0x04 0x10 0x04 0x11>; reset-names = "RST_MAG_MACV110_X4_T_00\0RST_MAG_MACV110_X4_T_01\0RST_MAG_MACV110_X4_T_02\0RST_MAG_MACV110_X4_T_03\0RST_MAG_MACV110_X4_T_04\0RST_MAG_MACV110_X4_T_05"; at_user = <0x01>; }; rst_mag_macv110_x4_cfg_group { rst_group_id = <0x02>; resets = <0x04 0x12 0x04 0x13 0x04 0x14 0x04 0x15 0x04 0x16 0x04 0x17 0x04 0x18 0x04 0x19 0x04 0x1a 0x04 0x1b 0x04 0x1c 0x04 0x1d 0x04 0x1e 0x04 0x1f 0x04 0x20 0x04 0x21 0x04 0x22 0x04 0x23 0x04 0x24 0x04 0x25 0x04 0x26 0x04 0x27 0x04 0x28 0x04 0x29>; reset-names = "RST_MAG_MACV110_X4_CFG_00\0RST_MAG_MACV110_X4_CFG_01\0RST_MAG_MACV110_X4_CFG_02\0RST_MAG_MACV110_X4_CFG_03\0RST_MAG_MACV110_X4_CFG_04\0RST_MAG_MACV110_X4_CFG_05\0RST_MAG_MACV110_X4_CFG_06\0RST_MAG_MACV110_X4_CFG_07\0RST_MAG_MACV110_X4_CFG_08\0RST_MAG_MACV110_X4_CFG_09\0RST_MAG_MACV110_X4_CFG_10\0RST_MAG_MACV110_X4_CFG_11\0RST_MAG_MACV110_X4_CFG_12\0RST_MAG_MACV110_X4_CFG_13\0RST_MAG_MACV110_X4_CFG_14\0RST_MAG_MACV110_X4_CFG_15\0RST_MAG_MACV110_X4_CFG_16\0RST_MAG_MACV110_X4_CFG_17\0RST_MAG_MACV110_X4_CFG_18\0RST_MAG_MACV110_X4_CFG_19\0RST_MAG_MACV110_X4_CFG_20\0RST_MAG_MACV110_X4_CFG_21\0RST_MAG_MACV110_X4_CFG_22\0RST_MAG_MACV110_X4_CFG_23"; at_user = <0x01>; }; rst_mag_macv110_x4_core_group { rst_group_id = <0x03>; resets = <0x04 0x2a 0x04 0x2b 0x04 0x2c 0x04 0x2d 0x04 0x2e 0x04 0x2f 0x04 0x30 0x04 0x31 0x04 0x32 0x04 0x33 0x04 0x34 0x04 0x35 0x04 0x36 0x04 0x37 0x04 0x38 0x04 0x39 0x04 0x3a 0x04 0x3b 0x04 0x3c 0x04 0x3d 0x04 0x3e 0x04 0x3f 0x04 0x40 0x04 0x41>; reset-names = "RST_MAG_MACV110_X4_CORE_00\0RST_MAG_MACV110_X4_CORE_01\0RST_MAG_MACV110_X4_CORE_02\0RST_MAG_MACV110_X4_CORE_03\0RST_MAG_MACV110_X4_CORE_04\0RST_MAG_MACV110_X4_CORE_05\0RST_MAG_MACV110_X4_CORE_06\0RST_MAG_MACV110_X4_CORE_07\0RST_MAG_MACV110_X4_CORE_08\0RST_MAG_MACV110_X4_CORE_09\0RST_MAG_MACV110_X4_CORE_10\0RST_MAG_MACV110_X4_CORE_11\0RST_MAG_MACV110_X4_CORE_12\0RST_MAG_MACV110_X4_CORE_13\0RST_MAG_MACV110_X4_CORE_14\0RST_MAG_MACV110_X4_CORE_15\0RST_MAG_MACV110_X4_CORE_16\0RST_MAG_MACV110_X4_CORE_17\0RST_MAG_MACV110_X4_CORE_18\0RST_MAG_MACV110_X4_CORE_19\0RST_MAG_MACV110_X4_CORE_20\0RST_MAG_MACV110_X4_CORE_21\0RST_MAG_MACV110_X4_CORE_22\0RST_MAG_MACV110_X4_CORE_23"; at_user = <0x01>; }; rst_mag_macv110_x1_t_group { rst_group_id = <0x04>; resets = <0x04 0x42 0x04 0x43>; reset-names = "RST_MAG_MACV110_X1_T_00\0RST_MAG_MACV110_X1_T_01"; at_user = <0x01>; }; rst_mag_macv110_x1_cfg_group { rst_group_id = <0x05>; resets = <0x04 0x44 0x04 0x45>; reset-names = "RST_MAG_MACV110_X1_CFG_00\0RST_MAG_MACV110_X1_CFG_01"; at_user = <0x01>; }; rst_mag_macv110_x1_core_group { rst_group_id = <0x06>; resets = <0x04 0x46 0x04 0x47>; reset-names = "RST_MAG_MACV110_X1_CORE_00\0RST_MAG_MACV110_X1_CORE_01"; at_user = <0x01>; }; port0@0 { port_id = <0x00>; port_info = <0x08 0x02 0x00 0x01>; interval_ms = <0x1f4>; optical_los = <0x00>; alos_bypass_flag = <0x00>; badeye_bypass_flag = <0x00>; adapt_act_power = <0x00>; first_link_redo_en = <0x00>; goodeye_filter_cnt = <0x00>; badeye_filter_cnt = <0x03>; dfe_false_time_ms = <0x00>; adapt_en_det = <0x00>; adapt_api = <0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00>; force_rf_insert_en = <0x01>; }; }; djtag0@0xFA0A0000 { compatible = "hisi_djtag"; djtag_id = <0x00>; reg = <0x00 0xfa0a0000 0x00 0x10000>; }; nandc@fc000000 { compatible = "hisi, v650-nandc"; reg = <0x00 0xfc000000 0x00 0x10000 0x08 0x00 0x00 0x10000>; reg-names = "nfc_reg_map\0nfc_internal_buffer"; clocks = <0x05 0x06>; clock-names = "CLK_NANDC_CLK0"; resets = <0x05 0x06>; reset-names = "RST_NANDC_RST0"; interrupts = <0x00 0x64 0x04>; host_id = <0x00>; nand-bus-width = <0x08>; nand-ecc-mode = "hw"; nand-ecc-step-size = <0x400>; plane_num = <0x01>; status = "okay"; skip_host_reset; nand-ecc-strength = <0x10>; bitflip_threshold = <0x08>; nfc_bus_type = <0x00>; timeout_prog = <0xffffff>; timeout_erase = <0xffffff>; nfc_dma_mode = <0x00>; nfc_pwidth = <0x466>; nfc_opidle = <0xffffff>; chip_num = <0x04>; randomizer = <0x00>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "na0"; reg = <0x00 0x10000000>; }; partition@0x10000000 { label = "na1"; reg = <0x10000000 0x30000000>; }; }; }; spi@FA400000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x00>; reg = <0x00 0xfa400000 0x00 0x10000>; interrupts = <0x00 0xf4 0x04>; clocks = <0x05 0x10>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x10>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; pinctrl-names = "default"; pinctrl-0 = <0x08>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x48>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x49>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; spi@FA410000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x01>; reg = <0x00 0xfa410000 0x00 0x10000>; interrupts = <0x00 0xf5 0x04>; clocks = <0x05 0x11>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x11>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x02>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; spi@FA420000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x02>; reg = <0x00 0xfa420000 0x00 0x10000>; interrupts = <0x00 0xf6 0x04>; clocks = <0x05 0x12>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x12>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x27>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x28>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; spi@FA430000 { compatible = "synopsis_spi"; #address-cells = <0x01>; #size-cells = <0x00>; bus-num = <0x03>; reg = <0x00 0xfa430000 0x00 0x10000>; interrupts = <0x00 0xf7 0x04>; clocks = <0x05 0x13>; clock-names = "CLK_SPI_CLK0"; resets = <0x05 0x13>; reset-names = "RST_SPI_RST0"; status = "okay"; num-cs = <0x04>; cs@0 { compatible = "rohm,dh2228fv"; reg = <0x00>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0xaa>; }; cs@1 { compatible = "rohm,dh2228fv"; reg = <0x01>; spi-max-frequency = <0x17d7840>; cs_type = <0x01>; gpio_id = <0x98>; }; cs@2 { compatible = "rohm,dh2228fv"; reg = <0x02>; spi-max-frequency = <0x17d7840>; }; cs@3 { compatible = "rohm,dh2228fv"; reg = <0x03>; spi-max-frequency = <0x17d7840>; }; }; espi0@FA470000 { compatible = "espi_v100"; resets = <0x05 0x09>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x09>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x00>; reg_info = <0x00 0xfa470000 0x00 0x10000>; remap_reg_info = <0x02 0x00 0x00 0x40000000>; status = "okay"; cs-nums = <0x04>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@2 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@3 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi1@FA480000 { compatible = "espi_v100"; resets = <0x05 0x0a>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0a>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x01>; reg_info = <0x00 0xfa480000 0x00 0x10000>; remap_reg_info = <0x02 0x40000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi2@FA490000 { compatible = "espi_v100"; resets = <0x05 0x0b>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0b>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x02>; reg_info = <0x00 0xfa490000 0x00 0x10000>; remap_reg_info = <0x02 0x80000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi3@FA4A0000 { compatible = "espi_v100"; resets = <0x05 0x0c>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0c>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x03>; reg_info = <0x00 0xfa4a0000 0x00 0x10000>; remap_reg_info = <0x02 0xc0000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi4@FA4B0000 { compatible = "espi_v100"; resets = <0x05 0x0d>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0d>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x04>; reg_info = <0x00 0xfa4b0000 0x00 0x10000>; remap_reg_info = <0x03 0x00 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi5@FA4C0000 { compatible = "espi_v100"; resets = <0x05 0x0e>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0e>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x05>; reg_info = <0x00 0xfa4c0000 0x00 0x10000>; remap_reg_info = <0x03 0x40000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; espi6@FA4D0000 { compatible = "espi_v100"; resets = <0x05 0x0f>; reset-names = "RST_ESPI_RST0"; clocks = <0x05 0x0f>; clock-names = "CLK_ESPI_CLK0"; bus-num = <0x06>; reg_info = <0x00 0xfa4d0000 0x00 0x10000>; remap_reg_info = <0x03 0x80000000 0x00 0x40000000>; status = "okay"; cs-nums = <0x02>; remap_mode = <0x01>; cs@0 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; cs@1 { remap_cfg = <0x01 0x03 0x00 0x00 0x01>; seq_cfg = <0x07 0x00 0x01 0x01 0x03 0xff>; }; }; localbus { compatible = "lbc"; reg = <0x00 0xfa080000 0x00 0x10000>; reg-names = "reg"; interrupts = <0x00 0x62 0x04>; bus_num = <0x00>; clocks = <0x05 0x18>; clock-names = "clk_lbus"; resets = <0x05 0x18>; reset-names = "RST_LBUS_RST0"; cnt = <0x01>; cfg0 = <0x00 0x00 0xfa080000 0x00 0x10000000>; }; usb_host@0xfc200000 { compatible = "xhci-platform"; reg = <0x00 0xfc200000 0x00 0x200000>; interrupts = <0x00 0x73 0x04>; dma-coherent; status = "okay"; }; usb_drd@0xfc400000 { compatible = "xhci-platform"; reg = <0x00 0xfc400000 0x00 0x200000>; interrupts = <0x00 0x71 0x04>; dma-coherent; status = "okay"; }; usb_hisi_0 { compatible = "hisilicon,udrv_usb"; clocks = <0x05 0x15>; clock-names = "host"; resets = <0x05 0x15 0x05 0x33>; reset-names = "host\0host_ext"; reg_base = <0x00 0xfc200000 0x00 0x40000>; host_no = <0x00>; status = "okay"; phy { phy_base = <0x00 0xfa820000 0x00 0x10000>; cfg_off = <0x100>; cfg_mask = <0xfff>; cfg_value = <0x302>; }; }; usb_hisi_1 { compatible = "hisilicon,udrv_usb"; clocks = <0x05 0x16>; clock-names = "host"; resets = <0x05 0x16 0x05 0x34>; reset-names = "host\0host_ext"; reg_base = <0x00 0xfc400000 0x00 0x40000>; host_no = <0x01>; status = "okay"; phy { phy_base = <0x00 0xfa830000 0x00 0x10000>; cfg_off = <0x100>; cfg_mask = <0xfff>; cfg_value = <0x302>; }; }; pcie@d8900000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x00 0x00 0x400000 0x00 0xd8900000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x1f7 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x1f9 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x1fa 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x1fb 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x1fc 0x04>; linux,pci-domain = <0x00>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x00 0x09 0x01>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x00>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x00>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x01>; }; }; pcie@d8980000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x20000000 0x00 0x400000 0x00 0xd8980000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x20800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x200 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x202 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x203 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x204 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x205 0x04>; linux,pci-domain = <0x01>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x02 0x09 0x03>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x01>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x01>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8a00000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x40000000 0x00 0x400000 0x00 0xd8a00000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x40800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x209 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x20b 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x20c 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x20d 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x20e 0x04>; linux,pci-domain = <0x02>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x04 0x09 0x05>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x02>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x02>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8a80000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x60000000 0x00 0x400000 0x00 0xd8a80000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x60800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x212 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x214 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x215 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x216 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x217 0x04>; linux,pci-domain = <0x03>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x06 0x09 0x07>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x03>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x03>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8b00000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0x80000000 0x00 0x400000 0x00 0xd8b00000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0x80800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x21b 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x21d 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x21e 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x21f 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x220 0x04>; linux,pci-domain = <0x04>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x08 0x09 0x09>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x04>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x02>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x04>; core-id = <0x00>; port-type = <0x01>; max-lanes = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8b80000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0xa0000000 0x00 0x400000 0x00 0xd8b80000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0xa0800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x224 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x226 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x227 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x228 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x229 0x04>; linux,pci-domain = <0x05>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x0a 0x09 0x0b>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x05>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x02>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x05>; core-id = <0x00>; port-type = <0x01>; max-lanes = <0x02>; target-speed = <0x03>; probe = <0x01>; }; }; pcie@d8c00000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0xc0000000 0x00 0x400000 0x00 0xd8c00000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0xc0800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x256 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x258 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x259 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x25a 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x25b 0x04>; linux,pci-domain = <0x06>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x0c 0x09 0x0d>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x06>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x06>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; pcie@d8c80000 { compatible = "hisilicon,udrv-pcie-ecam-dt"; reg = <0x0b 0xe0000000 0x00 0x400000 0x00 0xd8c80000 0x00 0x80000 0x00 0x700000 0x00 0x00>; reg-names = "config\0dbi\0msi"; bus-range = <0x00 0x03>; ranges = <0x82000000 0x00 0x00 0x0b 0xe0800000 0x00 0x1f800000>; #address-cells = <0x03>; #size-cells = <0x02>; device_type = "pci"; dma-coherent; msi-trans-type = <0x01>; interrupts = <0x00 0x25f 0x04>; #interrupt-cells = <0x01>; interrupt-map-mask = <0xf800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x261 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x262 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x263 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x264 0x04>; linux,pci-domain = <0x07>; core-version = <0x00>; clocks_num = <0x02>; clocks = <0x09 0x0e 0x09 0x0f>; clock-names = "CLK_PCIE_CLK0\0CLK_PCIE_CLK1"; resets_num = <0x01>; resets = <0x09 0x07>; reset-names = "RST_PCIE_RST0"; status = "okay"; port@0 { lanes-nums = <0x01>; max-lanes = <0x01>; max-speed = <0x03>; port-id = <0x00>; lport-id = <0x07>; core-id = <0x00>; port-type = <0x01>; target-speed = <0x01>; probe = <0x00>; }; }; gpio@fa540000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa540000 0x00 0x10000>; base = <0x00>; ngpios = <0x20>; host_id = <0x00>; interrupts = <0x00 0x75 0x04>; clocks = <0x05 0x23>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x23>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa550000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa550000 0x00 0x10000>; base = <0x20>; ngpios = <0x20>; host_id = <0x01>; interrupts = <0x00 0x76 0x04>; clocks = <0x05 0x24>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x24>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa560000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa560000 0x00 0x10000>; base = <0x40>; ngpios = <0x20>; host_id = <0x02>; interrupts = <0x00 0x77 0x04>; clocks = <0x05 0x25>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x25>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa570000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa570000 0x00 0x10000>; base = <0x60>; ngpios = <0x20>; host_id = <0x03>; interrupts = <0x00 0x78 0x04>; clocks = <0x05 0x26>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x26>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; phandle = <0x0c>; }; gpio@fa580000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa580000 0x00 0x10000>; base = <0x80>; ngpios = <0x20>; host_id = <0x04>; interrupts = <0x00 0x79 0x04>; clocks = <0x05 0x27>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x27>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa590000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa590000 0x00 0x10000>; base = <0xa0>; ngpios = <0x20>; host_id = <0x05>; interrupts = <0x00 0x7a 0x04>; clocks = <0x05 0x28>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x28>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa5A0000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa5a0000 0x00 0x10000>; base = <0xc0>; ngpios = <0x20>; host_id = <0x06>; interrupts = <0x00 0x7b 0x04>; clocks = <0x05 0x29>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x29>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@fa5B0000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfa5b0000 0x00 0x10000>; base = <0xe0>; ngpios = <0x20>; host_id = <0x07>; interrupts = <0x00 0x7c 0x04>; clocks = <0x05 0x2a>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x2a>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; phandle = <0x1d>; }; gpio@faa90000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfaa90000 0x00 0x10000>; base = <0x100>; ngpios = <0x20>; host_id = <0x08>; interrupts = <0x00 0xa5 0x04>; clocks = <0x05 0x2b>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x2b>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; gpio@faaa0000 { compatible = "hisilicon,udrv_gpio"; reg = <0x00 0xfaaa0000 0x00 0x10000>; base = <0x120>; ngpios = <0x20>; host_id = <0x09>; interrupts = <0x00 0xa6 0x04>; clocks = <0x05 0x2c>; clock-names = "CLK_GPIO_CLK0"; resets = <0x05 0x2c>; reset-names = "RST_GPIO_RST0"; gpio-controller; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; status = "okay"; skip_host_reset; }; i2c@fa380000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa380000 0x00 0x10000>; interrupts = <0x00 0x106 0x04>; clocks = <0x05 0x19>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x19>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x00>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x0a>; pinctrl-1 = <0x0b>; sda-gpios = <0x0c 0x09 0x00>; scl-gpios = <0x0c 0x0a 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa390000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa390000 0x00 0x10000>; interrupts = <0x00 0x107 0x04>; clocks = <0x05 0x1a>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1a>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x01>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x0d>; pinctrl-1 = <0x0e>; sda-gpios = <0x0c 0x0b 0x00>; scl-gpios = <0x0c 0x0c 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3b0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3b0000 0x00 0x10000>; interrupts = <0x00 0x109 0x04>; clocks = <0x05 0x1c>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1c>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x03>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x11>; pinctrl-1 = <0x12>; sda-gpios = <0x0c 0x1b 0x00>; scl-gpios = <0x0c 0x1a 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3c0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3c0000 0x00 0x10000>; interrupts = <0x00 0x10a 0x04>; clocks = <0x05 0x1d>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1d>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x04>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x13>; pinctrl-1 = <0x14>; sda-gpios = <0x0c 0x0d 0x00>; scl-gpios = <0x0c 0x0e 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3d0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3d0000 0x00 0x10000>; interrupts = <0x00 0x10b 0x04>; clocks = <0x05 0x1e>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1e>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x05>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x15>; pinctrl-1 = <0x16>; sda-gpios = <0x0c 0x0f 0x00>; scl-gpios = <0x0c 0x10 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3e0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3e0000 0x00 0x10000>; interrupts = <0x00 0x10c 0x04>; clocks = <0x05 0x1f>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x1f>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x06>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x17>; pinctrl-1 = <0x18>; sda-gpios = <0x0c 0x11 0x00>; scl-gpios = <0x0c 0x12 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@fa3f0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfa3f0000 0x00 0x10000>; interrupts = <0x00 0x10d 0x04>; clocks = <0x05 0x20>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x20>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x07>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x19>; pinctrl-1 = <0x1a>; sda-gpios = <0x0c 0x13 0x00>; scl-gpios = <0x0c 0x14 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@faab0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfaab0000 0x00 0x10000>; interrupts = <0x00 0x28e 0x04>; clocks = <0x05 0x21>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x21>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x08>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x1b>; pinctrl-1 = <0x1c>; sda-gpios = <0x1d 0x10 0x00>; scl-gpios = <0x1d 0x0f 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; i2c@faac0000 { compatible = "hisilicon,udrv_i2c_synopsys"; reg = <0x00 0xfaac0000 0x00 0x10000>; interrupts = <0x00 0x28f 0x04>; clocks = <0x05 0x22>; clock-names = "CLK_I2C_CLK0"; resets = <0x05 0x22>; reset-names = "RST_I2C_RST0"; clk_rate = <0xbebc200>; bus_id = <0x09>; pinctrl-names = "default\0gpio"; pinctrl-0 = <0x1e>; pinctrl-1 = <0x1f>; sda-gpios = <0x1d 0x12 0x00>; scl-gpios = <0x1d 0x11 0x00>; status = "okay"; clock-frequency = <0x186a0>; i2c-scl-rising-time-ns = <0x12c>; i2c-scl-falling-time-ns = <0x12c>; i2c-sda-hold-time-ns = <0x190>; i2c-digital-filter-width-ns = <0x19>; }; sfc0@0xfa5C0000 { compatible = "hisi, v120-sfc"; reg = <0x00 0xfa5c0000 0x00 0x10000>; reg-names = "reg"; interrupts = <0x00 0x8b 0x04>; host_id = <0x00>; clocks = <0x05 0x2d>; clock-names = "CLK_SFC_CLK0"; resets = <0x05 0x2d>; reset-names = "RST_SFC_RST0"; status = "okay"; skip_host_reset; flash@0 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x00>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios0"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test0"; reg = <0x1000000 0x100000>; }; }; }; flash@1 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x01>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios1"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env1"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test1"; reg = <0x1000000 0x100000>; }; }; }; }; sfc1@0xfa4e0000 { compatible = "hisi, v120-sfc"; reg = <0x00 0xfa4e0000 0x00 0x10000>; reg-names = "reg"; interrupts = <0x00 0x8c 0x04>; host_id = <0x01>; clocks = <0x05 0x2e>; clock-names = "CLK_SFC_CLK0"; resets = <0x05 0x2e>; reset-names = "RST_SFC_RST0"; status = "disable"; pinctrl-names = "default"; pinctrl-0 = <0x20>; flash@0 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x00>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios0"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test0"; reg = <0x1000000 0x100000>; }; }; }; flash@1 { compatible = "jedec,spi-nor"; sfc-rx-bus-width = <0x01>; sfc-tx-bus-width = <0x01>; cs = <0x01>; partitions { compatible = "fixed-partitions"; #address-cells = <0x01>; #size-cells = <0x01>; partition@0 { label = "bios1"; reg = <0x00 0x800000>; }; partition@800000 { label = "bootrom_env1"; reg = <0x800000 0x800000>; }; partition@900000 { label = "test1"; reg = <0x1000000 0x100000>; }; }; }; }; pmbus0@fa870000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa870000 0x00 0x10000>; pmbus_id = <0x00>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; pec_en = <0x00>; }; pmbus1@fa880000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa880000 0x00 0x10000>; pmbus_id = <0x01>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; }; pmbus2@fa890000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa890000 0x00 0x10000>; pmbus_id = <0x02>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; }; pmbus3@fa8a0000 { compatible = "hisilicon,udrv_pmbus"; reg = <0x00 0xfa8a0000 0x00 0x10000>; pmbus_id = <0x03>; clk_freq_mhz = <0xc8>; avs_wr_unlock_key = <0x5a5a5a5a>; pmbus_wr_unlock_key = <0x5a5a5a5a>; i2c_unlock_key = <0x5a5a5a5a>; status = "okay"; bus_freq_hz = <0x186a0>; scl_high_ratio = <0x32>; scl_low_timeout_ms = <0x1e>; scl_high_idle_us = <0x64>; sda_hold_time_ns = <0x271>; }; sata@0xd8500000 { compatible = "generic-ahci"; reg = <0x00 0xd8500000 0x00 0x100000>; interrupts = <0x00 0x1f3 0x04>; dma-coherent; status = "okay"; }; sata_dfx@0xd8500000 { compatible = "hisilicon,udrv_sata"; reg = <0x00 0xd8500000 0x00 0x100000>; host_id = <0x00>; tx-bitorder = <0x00>; rx-bitorder = <0x01>; clocks = <0x09 0x11>; clock-names = "CLK_SATA_CLK0"; resets = <0x09 0x09>; reset-names = "RST_SATA_RST0"; status = "okay"; }; pinctrl@FA860000 { compatible = "hisi,hi309a-pinctrl"; reg = <0x00 0xfa860000 0x00 0x10000>; status = "okay"; hisi309a-i2c-basic { i2c0_default { hisi,pins = <0xd8 0x30000 0x8dc 0x300fb 0x00 0xffffffff 0xdc 0x30000 0x8e0 0x300fb 0x00 0xffffffff>; phandle = <0x0a>; }; i2c0_gpio { hisi,pins = <0xd8 0x30000 0x8dc 0x300fb 0x06 0xffffffff 0xdc 0x30000 0x8e0 0x300fb 0x06 0xffffffff>; phandle = <0x0b>; }; i2c1_default { hisi,pins = <0x298 0x30000 0xab8 0x300fb 0x00 0xffffffff 0x29c 0x30000 0xabc 0x300fb 0x00 0xffffffff>; phandle = <0x0d>; }; i2c1_gpio { hisi,pins = <0x298 0x30000 0xab8 0x300fb 0x06 0xffffffff 0x29c 0x30000 0xabc 0x300fb 0x06 0xffffffff>; phandle = <0x0e>; }; i2c2_default { hisi,pins = <0x1d8 0x30000 0x9f8 0x300fb 0x01 0xffffffff 0x1d4 0x30000 0x9f4 0x300fb 0x01 0xffffffff>; phandle = <0x0f>; }; i2c2_gpio { hisi,pins = <0x1d8 0x30000 0x9f8 0x300fb 0x06 0xffffffff 0x1d4 0x30000 0x9f4 0x300fb 0x06 0xffffffff>; phandle = <0x10>; }; i2c3_default { hisi,pins = <0x3f0 0x30000 0xc24 0x300fb 0x01 0xffffffff 0x3ec 0x30000 0xc20 0x300fb 0x01 0xffffffff>; phandle = <0x11>; }; i2c3_gpio { hisi,pins = <0x3f0 0x30000 0xc24 0x300fb 0x06 0xffffffff 0x3ec 0x30000 0xc20 0x300fb 0x06 0xffffffff>; phandle = <0x12>; }; i2c4_default { hisi,pins = <0x200 0x30000 0xa20 0x300fb 0x02 0xffffffff 0x204 0x30000 0xa24 0x300fb 0x02 0xffffffff>; phandle = <0x13>; }; i2c4_gpio { hisi,pins = <0x200 0x30000 0xa20 0x300fb 0x06 0xffffffff 0x204 0x30000 0xa24 0x300fb 0x06 0xffffffff>; phandle = <0x14>; }; i2c5_default { hisi,pins = <0x220 0x30000 0xa40 0x300fb 0x01 0xffffffff 0x224 0x30000 0xa44 0x300fb 0x00 0xffffffff>; phandle = <0x15>; }; i2c5_gpio { hisi,pins = <0x220 0x30000 0xa40 0x300fb 0x06 0xffffffff 0x224 0x30000 0xa44 0x300fb 0x06 0xffffffff>; phandle = <0x16>; }; i2c6_default { hisi,pins = <0x12c 0x30000 0x934 0x300fb 0x01 0xffffffff 0x130 0x30000 0x938 0x300fb 0x01 0xffffffff>; phandle = <0x17>; }; i2c6_gpio { hisi,pins = <0x12c 0x30000 0x934 0x300fb 0x06 0xffffffff 0x130 0x30000 0x938 0x300fb 0x06 0xffffffff>; phandle = <0x18>; }; i2c7_default { hisi,pins = <0x2ac 0x30000 0xacc 0x300fb 0x01 0xffffffff 0x2b0 0x30000 0xad0 0x300fb 0x01 0xffffffff>; phandle = <0x19>; }; i2c7_gpio { hisi,pins = <0x2ac 0x30000 0xacc 0x300fb 0x06 0xffffffff 0x2b0 0x30000 0xad0 0x300fb 0x06 0xffffffff>; phandle = <0x1a>; }; i2c8_default { hisi,pins = <0x3f8 0x30000 0xc2c 0x300fb 0x01 0xffffffff 0x3f4 0x30000 0xc28 0x300fb 0x01 0xffffffff>; phandle = <0x1b>; }; i2c8_gpio { hisi,pins = <0x3f8 0x30000 0xc2c 0x300fb 0x06 0xffffffff 0x3f4 0x30000 0xc28 0x300fb 0x06 0xffffffff>; phandle = <0x1c>; }; i2c9_default { hisi,pins = <0x400 0x30000 0xc34 0x300fb 0x01 0xffffffff 0x3fc 0x30000 0xc30 0x300fb 0x01 0xffffffff>; phandle = <0x1e>; }; i2c9_gpio { hisi,pins = <0x400 0x30000 0xc34 0x300fb 0x06 0xffffffff 0x3fc 0x30000 0xc30 0x300fb 0x06 0xffffffff>; phandle = <0x1f>; }; }; hisi309a-sfc-basic { sfc1_default { hisi,pins = <0x0c 0x30000 0x810 0x300fb 0x01 0xffffffff 0x14 0x30000 0x818 0x300fb 0x01 0xffffffff 0x1c 0x30000 0x820 0x300fb 0x01 0xffffffff 0x30 0x30000 0x834 0x300fb 0x01 0xffffffff 0x3c 0x30000 0x840 0x300fb 0x01 0xffffffff 0x40 0x30000 0x844 0x300fb 0x01 0xffffffff 0x44 0x30000 0x848 0x300fb 0x01 0xffffffff 0x48 0x30000 0x84c 0x300fb 0x01 0xffffffff 0x4c 0x30000 0x850 0x300fb 0x01 0xffffffff>; phandle = <0x20>; }; }; hisi309a-spi-basic { spi0_default { hisi,pins = <0x3e0 0x30000 0xc14 0x300fb 0x06 0xffffffff 0x3e4 0x30000 0xc18 0x300fb 0x06 0xffffffff 0x3d4 0x30000 0xc08 0x300fb 0x00 0xffffffff 0x3d8 0x30000 0xc0c 0x300fb 0x00 0xffffffff 0x3dc 0x30000 0xc10 0x300fb 0x00 0xffffffff>; phandle = <0x08>; }; spi1_default { hisi,pins = <0xf4 0x30000 0x8f8 0x300fb 0x06 0xffffffff 0xe8 0x30000 0x8ec 0x300fb 0x01 0xffffffff 0xec 0x30000 0x8f0 0x300fb 0x01 0xffffffff 0xf0 0x30000 0x8f4 0x300fb 0x01 0xffffffff>; }; spi2_default { hisi,pins = <0x148 0x30000 0x954 0x300fb 0x00 0xffffffff 0x14c 0x30000 0x958 0x300fb 0x00 0xffffffff 0x144 0x30000 0x950 0x300fb 0x03 0xffffffff 0x170 0x30000 0x97c 0x300fb 0x03 0xffffffff 0x150 0x30000 0x95c 0x300fb 0x03 0xffffffff>; }; spi3_default { hisi,pins = <0x38c 0x30000 0xbb8 0x300fb 0x00 0xffffffff 0x390 0x20000 0xbbc 0x300fb 0x00 0xffffffff 0x380 0x30000 0xbac 0x300fb 0x03 0xffffffff 0x384 0x30000 0xbb0 0x300fb 0x03 0xffffffff 0x388 0x30000 0xbb4 0x300fb 0x02 0xffffffff>; }; }; }; tsensor@FA0D0000 { compatible = "tsensor"; reg = <0x00 0xfa0d0000 0x00 0x10000 0x00 0xfa0a0000 0x00 0x10000>; sensor_id = <0x00>; sensor_name = "tsensor0"; status = "okay"; force_init = <0x00>; trim_mode = <0x00>; low_thld = <0x00>; high_thld = <0x0f>; ultra_high_thld = <0x3ff>; sample_num = <0x00>; }; tsensor@FA0E0000 { compatible = "tsensor"; reg = <0x00 0xfa0e0000 0x00 0x10000 0x00 0xfa0a0000 0x00 0x10000>; sensor_id = <0x01>; sensor_name = "tsensor1"; status = "okay"; force_init = <0x00>; trim_mode = <0x00>; low_thld = <0x00>; high_thld = <0x0f>; ultra_high_thld = <0x3ff>; sample_num = <0x00>; }; memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x0 0x1A500000>, <0x0 0x20000000 0x0 0xA0000000>, <0x4 0xC0000000 0x1 0x40000000>; }; };
10-23
/dts-v1/; / { compatible = "xlnx,zynqmp"; #address-cells = <0x2>; #size-cells = <0x2>; cpus { #address-cells = <0x1>; #size-cells = <0x0>; cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <0x1>; reg = <0x0>; cpu-idle-states = <0x2>; clocks = <0x3 0xa>; phandle = <0x3a>; }; cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <0x1>; cpu-idle-states = <0x2>; phandle = <0x3b>; }; cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <0x1>; cpu-idle-states = <0x2>; phandle = <0x3c>; }; cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <0x1>; cpu-idle-states = <0x2>; phandle = <0x3d>; }; idle-states { entry-method = "psci"; cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <0x12c>; exit-latency-us = <0x258>; min-residency-us = <0x2710>; phandle = <0x2>; }; }; }; opp-table-cpu { compatible = "operating-points-v2"; opp-shared; phandle = <0x1>; opp00 { opp-hz = <0x0 0x4f7704c9>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp01 { opp-hz = <0x0 0x27bb8264>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp02 { opp-hz = <0x0 0x1a7d0198>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp03 { opp-hz = <0x0 0x13ddc132>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; }; zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <0x4>; interrupts = <0x0 0x23 0x4>; xlnx,ipi-id = <0x0>; #address-cells = <0x2>; #size-cells = <0x2>; ranges; phandle = <0x3e>; mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20 0x0 0xff9905e0 0x0 0x20 0x0 0xff990e80 0x0 0x20 0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <0x1>; xlnx,ipi-id = <0x4>; phandle = <0x5>; }; }; dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; phandle = <0x3f>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <0x4>; interrupts = <0x0 0x8f 0x4 0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; phandle = <0xc>; zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <0x4>; interrupts = <0x0 0x23 0x4>; mboxes = <0x5 0x0 0x5 0x1>; mbox-names = "tx", "rx"; phandle = <0x40>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <0x1>; #size-cells = <0x1>; soc_revision@0 { reg = <0x0 0x4>; phandle = <0x41>; }; efuse_dna@c { reg = <0xc 0xc>; phandle = <0x42>; }; efuse_usr0@20 { reg = <0x20 0x4>; phandle = <0x43>; }; efuse_usr1@24 { reg = <0x24 0x4>; phandle = <0x44>; }; efuse_usr2@28 { reg = <0x28 0x4>; phandle = <0x45>; }; efuse_usr3@2c { reg = <0x2c 0x4>; phandle = <0x46>; }; efuse_usr4@30 { reg = <0x30 0x4>; phandle = <0x47>; }; efuse_usr5@34 { reg = <0x34 0x4>; phandle = <0x48>; }; efuse_usr6@38 { reg = <0x38 0x4>; phandle = <0x49>; }; efuse_usr7@3c { reg = <0x3c 0x4>; phandle = <0x4a>; }; efuse_miscusr@40 { reg = <0x40 0x4>; phandle = <0x4b>; }; efuse_chash@50 { reg = <0x50 0x4>; phandle = <0x4c>; }; efuse_pufmisc@54 { reg = <0x54 0x4>; phandle = <0x4d>; }; efuse_sec@58 { reg = <0x58 0x4>; phandle = <0x4e>; }; efuse_spkid@5c { reg = <0x5c 0x4>; phandle = <0x4f>; }; efuse_ppk0hash@a0 { reg = <0xa0 0x30>; phandle = <0x50>; }; efuse_ppk1hash@d0 { reg = <0xd0 0x30>; phandle = <0x51>; }; }; pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; clocks = <0x3 0x29>; phandle = <0xb>; }; zynqmp-aes { compatible = "xlnx,zynqmp-aes"; phandle = <0x52>; }; reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <0x1>; phandle = <0xe>; }; pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; phandle = <0x53>; }; sha384 { compatible = "xlnx,zynqmp-keccak-384"; phandle = <0x54>; }; zynqmp-rsa { compatible = "xlnx,zynqmp-rsa"; phandle = <0x55>; }; gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <0x2>; phandle = <0x16>; }; clock-controller { u-boot,dm-pre-reloc; #clock-cells = <0x1>; compatible = "xlnx,zynqmp-clk"; clocks = <0x6 0x7 0x8 0x9 0xa>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; phandle = <0x3>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <0x4>; interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga-full { compatible = "fpga-region"; fpga-mgr = <0xb>; #address-cells = <0x2>; #size-cells = <0x2>; ranges; phandle = <0x56>; }; axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <0x2>; #size-cells = <0x2>; ranges; phandle = <0x57>; can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0x0 0x17 0x4>; interrupt-parent = <0x4>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <0xc 0x2f>; clocks = <0x3 0x3f 0x3 0x1f>; phandle = <0x58>; }; can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "okay"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0x0 0x18 0x4>; interrupt-parent = <0x4>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <0xc 0x30>; clocks = <0x3 0x40 0x3 0x1f>; phandle = <0x59>; }; cci@fd6e0000 { compatible = "arm,cci-400"; status = "okay"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <0x1>; #size-cells = <0x1>; phandle = <0x5a>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4>; }; }; dma-controller@fd500000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7c 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14e8>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5b>; }; dma-controller@fd510000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7d 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14e9>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5c>; }; dma-controller@fd520000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7e 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ea>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5d>; }; dma-controller@fd530000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7f 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14eb>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5e>; }; dma-controller@fd540000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x80 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ec>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5f>; }; dma-controller@fd550000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x81 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ed>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x60>; }; dma-controller@fd560000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x82 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ee>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x61>; }; dma-controller@fd570000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x83 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ef>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x62>; }; interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <0x3>; reg = <0x0 0xf9010000 0x0 0x10000 0x0 0xf9020000 0x0 0x20000 0x0 0xf9040000 0x0 0x20000 0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <0x4>; interrupts = <0x1 0x9 0xf04>; num_cpus = <0x2>; num_interrupts = <0x60>; phandle = <0x4>; }; gpu@fd4b0000 { status = "okay"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <0x4>; interrupts = <0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <0xc 0x3a>; clocks = <0x3 0x18 0x3 0x19 0x3 0x1a>; xlnx,tz-nonsecure = <0x1>; phandle = <0x63>; }; dma-controller@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x4d 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x64>; }; dma-controller@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x4e 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x65>; }; dma-controller@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x4f 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x66>; }; dma-controller@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x50 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x67>; }; dma-controller@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x51 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x68>; }; dma-controller@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x52 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x69>; }; dma-controller@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x53 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x6a>; }; dma-controller@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x54 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x6b>; }; memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <0x4>; interrupts = <0x0 0x70 0x4>; phandle = <0x6c>; }; nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <0x4>; interrupts = <0x0 0xe 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x872>; power-domains = <0xc 0x2c>; clocks = <0x3 0x3c 0x3 0x1f>; phandle = <0x6d>; }; ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x874>; power-domains = <0xc 0x1d>; resets = <0xe 0x1d>; clocks = <0x3 0x1f 0x3 0x68 0x3 0x2d 0x3 0x31 0x3 0x2c>; phandle = <0x6e>; }; ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x3b 0x4 0x0 0x3b 0x4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x875>; power-domains = <0xc 0x1e>; resets = <0xe 0x1e>; clocks = <0x3 0x1f 0x3 0x69 0x3 0x2e 0x3 0x32 0x3 0x2c>; phandle = <0x6f>; }; ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x876>; power-domains = <0xc 0x1f>; resets = <0xe 0x1f>; clocks = <0x3 0x1f 0x3 0x6a 0x3 0x2f 0x3 0x33 0x3 0x2c>; phandle = <0x70>; }; ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x877>; power-domains = <0xc 0x20>; resets = <0xe 0x20>; clocks = <0x3 0x1f 0x3 0x6b 0x3 0x30 0x3 0x34 0x3 0x2c>; phy-mode = "rgmii-id"; xlnx,ptp-enet-clock = <0x0>; local-mac-address = [ff ff ff ff ff ff]; phy-handle = <0xf>; phandle = <0x71>; ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; phandle = <0xf>; }; }; gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <0x4>; interrupts = <0x0 0x10 0x4>; interrupt-controller; #interrupt-cells = <0x2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <0xc 0x2e>; clocks = <0x3 0x1f>; emio-gpio-width = <0x20>; gpio-mask-high = <0x0>; gpio-mask-low = <0x5600>; phandle = <0x1f>; }; i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x11 0x4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x25>; clocks = <0x3 0x3d>; clock-frequency = <0x61a80>; phandle = <0x72>; }; i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x12 0x4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x26>; clocks = <0x3 0x3e>; clock-frequency = <0x61a80>; phandle = <0x73>; }; memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0xa 0x4>; phandle = <0x74>; }; perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0x0 0x19 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x1>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x1>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0x8>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1f>; phandle = <0x75>; }; perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0x0 0x7b 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x6>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x0>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0xa>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1c>; phandle = <0x76>; }; perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0x0 0x7b 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x1>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x0>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0x8>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1c>; phandle = <0x77>; }; perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0x0 0x19 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x1>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x1>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0x8>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1f>; phandle = <0x78>; }; pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; msi-controller; device_type = "pci"; interrupt-parent = <0x4>; interrupts = <0x0 0x76 0x4 0x0 0x75 0x4 0x0 0x74 0x4 0x0 0x73 0x4 0x0 0x72 0x4>; interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <0x10>; reg = <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd480000 0x0 0x1000 0x80 0x0 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x2000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000 0x43000000 0x6 0x0 0x6 0x0 0x2 0x0>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x0 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 0x11 0x1 0x0 0x0 0x0 0x2 0x11 0x2 0x0 0x0 0x0 0x3 0x11 0x3 0x0 0x0 0x0 0x4 0x11 0x4>; iommus = <0xd 0x4d0>; power-domains = <0xc 0x3b>; clocks = <0x3 0x17>; phandle = <0x10>; legacy-interrupt-controller { interrupt-controller; #address-cells = <0x0>; #interrupt-cells = <0x1>; phandle = <0x11>; }; }; spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupts = <0x0 0xf 0x4>; interrupt-parent = <0x4>; num-cs = <0x1>; reg = <0x0 0xff0f0000 0x0 0x1000 0x0 0xc0000000 0x0 0x8000000>; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x873>; power-domains = <0xc 0x2d>; clocks = <0x3 0x35 0x3 0x1f>; is-dual = <0x1>; spi-rx-bus-width = <0x4>; spi-tx-bus-width = <0x4>; phandle = <0x79>; flash@0 { spi-tx-bus-width = <0x4>; spi-rx-bus-width = <0x4>; compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; #address-cells = <0x1>; #size-cells = <0x1>; spi-max-frequency = <0x2faf080>; phandle = <0x7a>; partition@0 { label = "qspi-boot"; reg = <0x0 0x1e00000>; }; partition@1 { label = "qspi-bootenv"; reg = <0x1e00000 0x40000>; }; partition@2 { label = "qspi-kernel"; reg = <0x1e40000 0x2140000>; }; partition@3 { label = "qspi-bootscr"; reg = <0x3f80000 0x80000>; }; partition@0x00000000 { label = "boot"; reg = <0x0 0x1e00000>; }; partition@0x01000000 { label = "bootenv"; reg = <0x1e00000 0x40000>; }; partition@0x00140000 { label = "kernel"; reg = <0x1e40000 0x2140000>; }; partition@0x01240000 { label = "bootscr"; reg = <0x3f80000 0x80000>; }; }; }; phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "okay"; reg = <0x0 0xfd400000 0x0 0x40000 0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <0x4>; clocks = <0x12 0x13 0x14 0x15>; clock-names = "ref0", "ref1", "ref2", "ref3"; phandle = <0x1a>; }; rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <0x4>; interrupts = <0x0 0x1a 0x4 0x0 0x1b 0x4>; interrupt-names = "alarm", "sec"; calibration = <0x7fff>; phandle = <0x7b>; }; ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "okay"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <0x4>; interrupts = <0x0 0x85 0x4>; power-domains = <0xc 0x1c>; resets = <0xe 0x10>; clocks = <0x3 0x16>; xlnx,tz-nonsecure-sata0 = <0x0>; xlnx,tz-nonsecure-sata1 = <0x0>; phandle = <0x7c>; }; mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x30 0x4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0x0>; iommus = <0xd 0x870>; power-domains = <0xc 0x27>; #clock-cells = <0x1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <0xe 0x26>; clocks = <0x3 0x36 0x3 0x1f>; assigned-clocks = <0x3 0x36>; phandle = <0x7d>; }; mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x31 0x4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0x1>; iommus = <0xd 0x871>; power-domains = <0xc 0x28>; #clock-cells = <0x1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <0xe 0x27>; clocks = <0x3 0x37 0x3 0x1f>; assigned-clocks = <0x3 0x37>; clock-frequency = <0xb2cbcae>; xlnx,mio-bank = <0x1>; phandle = <0x7e>; }; smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <0x1>; status = "disabled"; #global-interrupts = <0x1>; interrupt-parent = <0x4>; interrupts = <0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4>; phandle = <0xd>; }; spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x13 0x4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x23>; clocks = <0x3 0x3a 0x3 0x1f>; is-decoded-cs = <0x0>; num-cs = <0x1>; phandle = <0x7f>; spidev@0x00 { compatible = "rohm,dh2228fv"; spi-max-frequency = <0xf4240>; reg = <0x0>; }; }; spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x14 0x4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x24>; clocks = <0x3 0x3b 0x3 0x1f>; phandle = <0x80>; }; timer@ff110000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x24 0x4 0x0 0x25 0x4 0x0 0x26 0x4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x18>; clocks = <0x3 0x1f>; phandle = <0x81>; }; timer@ff120000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x27 0x4 0x0 0x28 0x4 0x0 0x29 0x4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x19>; clocks = <0x3 0x1f>; phandle = <0x82>; }; timer@ff130000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x2a 0x4 0x0 0x2b 0x4 0x0 0x2c 0x4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x1a>; clocks = <0x3 0x1f>; phandle = <0x83>; }; timer@ff140000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x2d 0x4 0x0 0x2e 0x4 0x0 0x2f 0x4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x1b>; clocks = <0x3 0x1f>; phandle = <0x84>; }; serial@ff000000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x15 0x4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <0xc 0x21>; clocks = <0x3 0x38 0x3 0x1f>; cts-override; device_type = "serial"; port-number = <0x0>; phandle = <0x85>; }; serial@ff010000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x16 0x4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <0xc 0x22>; clocks = <0x3 0x39 0x3 0x1f>; cts-override; device_type = "serial"; port-number = <0x2>; phandle = <0x86>; }; usb0@ff9d0000 { #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <0xc 0x16>; resets = <0xe 0x3b 0xe 0x3d 0xe 0x3f>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <0x16 0x1 0x1>; ranges; clocks = <0x3 0x20 0x3 0x22>; assigned-clocks = <0x3 0x20 0x3 0x22>; xlnx,tz-nonsecure = <0x1>; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phandle = <0x87>; usb@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <0x4>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0x0 0x41 0x4 0x0 0x45 0x4 0x0 0x4b 0x4>; iommus = <0xd 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-reset-on-resume; snps,xhci-stream-quirk; clocks = <0x3 0x22>; phandle = <0x88>; }; }; usb1@ff9e0000 { #address-cells = <0x2>; #size-cells = <0x2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <0xc 0x17>; resets = <0xe 0x3c 0xe 0x3e 0xe 0x40>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; clocks = <0x3 0x21 0x3 0x22>; assigned-clocks = <0x3 0x21 0x3 0x22>; phandle = <0x89>; usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <0x4>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0x0 0x46 0x4 0x0 0x4a 0x4 0x0 0x4c 0x4>; iommus = <0xd 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-reset-on-resume; snps,xhci-stream-quirk; clocks = <0x3 0x22>; phandle = <0x8a>; }; }; watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x71 0x1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <0x3c>; reset-on-timeout; clocks = <0x3 0x4b>; phandle = <0x8b>; }; watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x34 0x1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <0xa>; clocks = <0x3 0x70>; phandle = <0x8c>; }; ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x38 0x4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <0x2>; #size-cells = <0x2>; #io-channel-cells = <0x1>; ranges; clocks = <0x3 0x46>; phandle = <0x8d>; ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "okay"; reg = <0x0 0xffa50800 0x0 0x400>; phandle = <0x8e>; }; ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "okay"; reg = <0x0 0xffa50c00 0x0 0x400>; phandle = <0x8f>; }; }; dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "okay"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0x0 0x7a 0x4>; interrupt-parent = <0x4>; clock-names = "axi_clk"; power-domains = <0xc 0x29>; dma-channels = <0x6>; iommus = <0xd 0xce4>; #dma-cells = <0x1>; clocks = <0x3 0x14>; assigned-clocks = <0x3 0x14>; phandle = <0x18>; }; dp_aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; phandle = <0x17>; }; display@fd4a0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "okay"; reg = <0x0 0xfd4a0000 0x0 0x1000 0x0 0xfd4aa000 0x0 0x1000 0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <0x17>; interrupts = <0x0 0x77 0x4>; interrupt-parent = <0x4>; iommus = <0xd 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <0xc 0x29>; resets = <0xe 0x3>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <0x18 0x0 0x18 0x1 0x18 0x2 0x18 0x3>; clocks = <0x19 0x3 0x11 0x3 0x10>; assigned-clocks = <0x3 0x12 0x3 0x11 0x3 0x10>; phy-names = "dp-phy0", "dp-phy1"; phys = <0x1a 0x1 0x6 0x0 0x3 0x1a 0x0 0x6 0x1 0x3>; xlnx,max-lanes = <0x2>; phandle = <0x90>; i2c-bus { }; zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; clocks = <0x3 0x11>; status = "okay"; phandle = <0x1d>; }; zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <0x18 0x4>; dma-names = "tx"; status = "okay"; phandle = <0x1b>; }; zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <0x18 0x5>; dma-names = "tx"; status = "okay"; phandle = <0x1c>; }; zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <0x1b 0x1c>; xlnx,dp-snd-codec = <0x1d>; status = "okay"; phandle = <0x91>; }; }; }; fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x47>; phandle = <0x92>; }; fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x48>; phandle = <0x93>; }; fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x49>; phandle = <0x94>; }; fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x4a>; phandle = <0x95>; }; pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x1fc9350>; phandle = <0x6>; }; video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x1fc9f08>; phandle = <0x7>; }; pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x0>; phandle = <0x8>; }; gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x66ff300>; phandle = <0xa>; }; aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x19bfcc0>; phandle = <0x9>; }; dp_aclk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x5f5e100>; clock-accuracy = <0x64>; phandle = <0x19>; }; amba_pl@0 { #address-cells = <0x2>; #size-cells = <0x2>; compatible = "simple-bus"; ranges; phandle = <0x96>; i2c@80090000 { #address-cells = <0x1>; #size-cells = <0x0>; clock-names = "s_axi_aclk"; clocks = <0x1e>; compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; interrupt-names = "iic2intc_irpt"; interrupt-parent = <0x4>; interrupts = <0x0 0x6e 0x4>; reg = <0x0 0x80090000 0x0 0x10000>; phandle = <0x97>; sensor@1a { compatible = "sony,imx274"; reg = <0x1a>; #address-cells = <0x1>; #size-cells = <0x0>; reset-gpios = <0x1f 0x5a 0x1>; phandle = <0x98>; port@0 { reg = <0x0>; endpoint { remote-endpoint = <0x20>; phandle = <0x2d>; }; }; }; }; serial@80000000 { clock-names = "s_axi_aclk"; clocks = <0x3 0x47>; compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a"; current-speed = <0x1c200>; device_type = "serial"; interrupt-names = "interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x68 0x1>; port-number = <0x1>; reg = <0x0 0x80000000 0x0 0x10000>; xlnx,baudrate = <0x1c200>; xlnx,data-bits = <0x8>; xlnx,odd-parity = <0x0>; xlnx,s-axi-aclk-freq-hz-d = "99.990005"; xlnx,use-parity = <0x0>; phandle = <0x99>; }; dpuczdx8g@8f000000 { clock-names = "s_axi_aclk", "dpu_2x_clk", "m_axi_dpu_aclk"; clocks = <0x3 0x47 0x21 0x22>; compatible = "xlnx,dpuczdx8g-4.1"; interrupt-names = "dpu0_interrupt", "sfm_interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x59 0x4 0x0 0x5c 0x4>; reg = <0x0 0x8f000000 0x0 0x1000000>; phandle = <0x9a>; }; misc_clk_0 { #clock-cells = <0x0>; clock-frequency = <0x26bd3898>; compatible = "fixed-clock"; phandle = <0x21>; }; misc_clk_1 { #clock-cells = <0x0>; clock-frequency = <0x135e9c4c>; compatible = "fixed-clock"; phandle = <0x22>; }; v_frmbuf_wr@80030000 { #dma-cells = <0x1>; clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2"; interrupt-names = "interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x6b 0x4>; reg = <0x0 0x80030000 0x0 0x10000>; reset-gpios = <0x1f 0x58 0x1>; xlnx,dma-addr-width = <0x20>; xlnx,dma-align = <0x10>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,pixels-per-clock = <0x2>; xlnx,s-axi-ctrl-addr-width = <0x7>; xlnx,s-axi-ctrl-data-width = <0x20>; xlnx,vid-formats = "bgr888", "uyvy", "vuy888", "yuyv", "y_u_v8"; xlnx,video-width = <0x8>; phandle = <0x36>; }; v_hdmi_rx_ss@80010000 { clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk"; clocks = <0x3 0x47 0x23 0x3 0x48 0x24 0x3 0x48>; compatible = "xlnx,v-hdmi-rx-ss-3.2", "xlnx,v-hdmi-rx-ss-3.1"; interrupt-names = "irq"; interrupt-parent = <0x4>; interrupts = <0x0 0x69 0x4>; phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2"; phys = <0x25 0x0 0x1 0x1 0x0 0x26 0x0 0x1 0x1 0x0 0x27 0x0 0x1 0x1 0x0>; reg = <0x0 0x80010000 0x0 0x10000>; xlnx,edid-ram-size = <0x100>; xlnx,input-pixels-per-clock = <0x2>; xlnx,max-bits-per-component = <0x8>; phandle = <0x9b>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0x9c>; port@0 { reg = <0x0>; xlnx,video-format = <0x0>; xlnx,video-width = <0xa>; phandle = <0x9d>; endpoint { remote-endpoint = <0x28>; phandle = <0x37>; }; }; }; }; misc_clk_2 { #clock-cells = <0x0>; clock-frequency = <0x8d9ee20>; compatible = "fixed-clock"; phandle = <0x23>; }; misc_clk_3 { #clock-cells = <0x0>; clock-frequency = <0x11b3dc40>; compatible = "fixed-clock"; phandle = <0x24>; }; vid_phy_controller@80020000 { clock-names = "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtsouthrefclk0_in", "gtsouthrefclk0_odiv2_in", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk", "dru-clk"; clocks = <0x29 0x29 0x29 0x29 0x23 0x3 0x47 0x3 0x47 0x3 0x47 0x2a>; compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1"; interrupt-names = "irq"; interrupt-parent = <0x4>; interrupts = <0x0 0x6a 0x4>; reg = <0x0 0x80020000 0x0 0x10000>; xlnx,hdmi-fast-switch = <0x1>; xlnx,input-pixels-per-clock = <0x2>; xlnx,nidru = <0x1>; xlnx,nidru-refclk-sel = <0x4>; xlnx,rx-no-of-channels = <0x3>; xlnx,rx-pll-selection = <0x0>; xlnx,rx-protocol = <0x1>; xlnx,rx-refclk-sel = <0x1>; xlnx,transceiver-type = <0x5>; xlnx,transceiver-width = <0x2>; xlnx,tx-buffer-bypass = <0x1>; xlnx,tx-no-of-channels = <0x3>; xlnx,tx-pll-selection = <0x6>; xlnx,tx-protocol = <0x3>; xlnx,tx-refclk-sel = <0x1>; xlnx,use-gt-ch4-hdmi = <0x0>; phandle = <0x9e>; vphy_lane@0 { #phy-cells = <0x4>; phandle = <0x25>; }; vphy_lane@1 { #phy-cells = <0x4>; phandle = <0x26>; }; vphy_lane@2 { #phy-cells = <0x4>; phandle = <0x27>; }; }; misc_clk_4 { #clock-cells = <0x0>; clock-frequency = <0x5f5e100>; compatible = "fixed-clock"; phandle = <0x29>; }; mipi_csi2_rx_subsystem@80040000 { clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk"; clocks = <0x3 0x47 0x2b 0x3 0x48>; compatible = "xlnx,mipi-csi2-rx-subsystem-5.0"; interrupt-names = "csirxss_csi_irq"; interrupt-parent = <0x4>; interrupts = <0x0 0x6c 0x4>; reg = <0x0 0x80040000 0x0 0x1000>; xlnx,axis-tdata-width = <0x20>; xlnx,csi-pxl-format = <0x2b>; xlnx,en-active-lanes; xlnx,max-lanes = <0x4>; xlnx,ppc = <0x2>; xlnx,vc = <0x4>; xlnx,vfb; phandle = <0x9f>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xa0>; port@1 { reg = <0x1>; xlnx,cfa-pattern = "rggb"; xlnx,video-format = <0xc>; xlnx,video-width = <0x8>; phandle = <0xa1>; endpoint { remote-endpoint = <0x2c>; phandle = <0x2f>; }; }; port@0 { reg = <0x0>; xlnx,cfa-pattern = "rggb"; xlnx,video-format = <0xc>; xlnx,video-width = <0x8>; phandle = <0xa2>; endpoint { data-lanes = <0x1 0x2 0x3 0x4>; remote-endpoint = <0x2d>; phandle = <0x20>; }; }; }; }; misc_clk_5 { #clock-cells = <0x0>; clock-frequency = <0xbeb73e0>; compatible = "fixed-clock"; phandle = <0x2b>; }; v_demosaic@80050000 { clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-demosaic-1.1", "xlnx,v-demosaic"; reg = <0x0 0x80050000 0x0 0x10000>; reset-gpios = <0x1f 0x55 0x1>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,s-axi-ctrl-addr-width = <0x6>; xlnx,s-axi-ctrl-data-width = <0x20>; phandle = <0xa3>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xa4>; port@1 { reg = <0x1>; xlnx,cfa-pattern = "rggb"; xlnx,video-width = <0x8>; phandle = <0xa5>; endpoint { remote-endpoint = <0x2e>; phandle = <0x31>; }; }; port@0 { reg = <0x0>; xlnx,cfa-pattern = "rggb"; xlnx,video-width = <0x8>; phandle = <0xa6>; endpoint { remote-endpoint = <0x2f>; phandle = <0x2c>; }; }; }; }; v_frmbuf_wr@80060000 { #dma-cells = <0x1>; clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2"; interrupt-names = "interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x6d 0x4>; reg = <0x0 0x80060000 0x0 0x10000>; reset-gpios = <0x1f 0x50 0x1>; xlnx,dma-addr-width = <0x20>; xlnx,dma-align = <0x10>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,pixels-per-clock = <0x2>; xlnx,s-axi-ctrl-addr-width = <0x7>; xlnx,s-axi-ctrl-data-width = <0x20>; xlnx,vid-formats = "bgr888", "uyvy", "y8", "yuyv"; xlnx,video-width = <0x8>; phandle = <0x38>; }; v_gamma_lut@80070000 { clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-gamma-lut-1.1", "xlnx,v-gamma-lut"; reg = <0x0 0x80070000 0x0 0x10000>; reset-gpios = <0x1f 0x56 0x1>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,s-axi-ctrl-addr-width = <0xd>; xlnx,s-axi-ctrl-data-width = <0x20>; phandle = <0xa7>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xa8>; port@1 { reg = <0x1>; xlnx,video-width = <0x8>; phandle = <0xa9>; endpoint { remote-endpoint = <0x30>; phandle = <0x33>; }; }; port@0 { reg = <0x0>; xlnx,video-width = <0x8>; phandle = <0xaa>; endpoint { remote-endpoint = <0x31>; phandle = <0x2e>; }; }; }; }; v_proc_ss@80080000 { clock-names = "aclk"; clocks = <0x3 0x48>; compatible = "xlnx,v-vpss-csc"; reg = <0x0 0x80080000 0x0 0x10000>; reset-gpios = <0x1f 0x54 0x1>; xlnx,colorspace-support = <0x2>; xlnx,csc-enable-window = "false"; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,num-video-components = <0x3>; xlnx,samples-per-clk = <0x2>; xlnx,topology = <0x3>; xlnx,use-uram = <0x0>; xlnx,video-width = <0x8>; phandle = <0xab>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xac>; port@1 { reg = <0x1>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xad>; endpoint { remote-endpoint = <0x32>; phandle = <0x35>; }; }; port@0 { reg = <0x0>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xae>; endpoint { remote-endpoint = <0x33>; phandle = <0x30>; }; }; }; }; v_proc_ss@800c0000 { clock-names = "aclk_axis", "aclk_ctrl"; clocks = <0x3 0x48 0x3 0x48>; compatible = "xlnx,v-vpss-scaler-2.2"; reg = <0x0 0x800c0000 0x0 0x40000>; reset-gpios = <0x1f 0x52 0x1>; xlnx,colorspace-support = <0x1>; xlnx,csc-enable-window = "true"; xlnx,enable-csc = "true"; xlnx,h-scaler-phases = <0x40>; xlnx,h-scaler-taps = <0x8>; xlnx,max-height = <0x870>; xlnx,max-num-phases = <0x40>; xlnx,max-width = <0xf00>; xlnx,num-hori-taps = <0x8>; xlnx,num-vert-taps = <0x8>; xlnx,pix-per-clk = <0x2>; xlnx,samples-per-clk = <0x2>; xlnx,scaler-algorithm = <0x2>; xlnx,topology = <0x0>; xlnx,use-uram = <0x0>; xlnx,v-scaler-phases = <0x40>; xlnx,v-scaler-taps = <0x8>; xlnx,video-width = <0x8>; phandle = <0xaf>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xb0>; port@1 { reg = <0x1>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xb1>; endpoint { remote-endpoint = <0x34>; phandle = <0x39>; }; }; port@0 { reg = <0x0>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xb2>; endpoint { remote-endpoint = <0x35>; phandle = <0x32>; }; }; }; }; vcap_hier_hdmirx20_v_hdmi_rx_ss_0 { compatible = "xlnx,video"; dma-names = "port0"; dmas = <0x36 0x0>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xb3>; port@0 { direction = "input"; reg = <0x0>; phandle = <0xb4>; endpoint { remote-endpoint = <0x37>; phandle = <0x28>; }; }; }; }; vcap_hier_mipi_rx0_v_proc_ss_1 { compatible = "xlnx,video"; dma-names = "port0"; dmas = <0x38 0x0>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xb5>; port@0 { direction = "input"; reg = <0x0>; phandle = <0xb6>; endpoint { remote-endpoint = <0x39>; phandle = <0x34>; }; }; }; }; vid_s_axi_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x5f5b9f0>; phandle = <0x1e>; }; }; chosen { bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; stdout-path = "serial0:115200n8"; }; aliases { ethernet0 = "/axi/ethernet@ff0e0000"; i2c0 = "/axi/i2c@ff020000"; i2c1 = "/axi/i2c@ff030000"; i2c2 = "/amba_pl@0/i2c@80090000"; serial0 = "/axi/serial@ff000000"; serial1 = "/axi/serial@ff010000"; serial2 = "/amba_pl@0/serial@80000000"; spi0 = "/axi/spi@ff0f0000"; spi1 = "/axi/spi@ff040000"; }; memory { device_type = "memory"; reg = <0x0 0x0 0x0 0x7ff00000 0x8 0x0 0x0 0x80000000>; }; psgtr_ref_0 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x5f5e100>; phandle = <0x12>; }; psgtr_ref_1 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x7735940>; phandle = <0x13>; }; psgtr_ref_2 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x18cba80>; phandle = <0x14>; }; psgtr_ref_3 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x19bfcc0>; phandle = <0x15>; }; druclk { #clock-cells = <0x0>; clock-frequency = <0x9502f90>; compatible = "fixed-clock"; phandle = <0x2a>; }; __symbols__ { cpu0 = "/cpus/cpu@0"; cpu1 = "/cpus/cpu@1"; cpu2 = "/cpus/cpu@2"; cpu3 = "/cpus/cpu@3"; CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0"; cpu_opp_table = "/opp-table-cpu"; zynqmp_ipi = "/zynqmp_ipi"; ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff990400"; dcc = "/dcc"; zynqmp_firmware = "/firmware/zynqmp-firmware"; zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power"; soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0"; efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c"; efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20"; efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24"; efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28"; efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c"; efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30"; efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34"; efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38"; efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c"; efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40"; efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50"; efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54"; efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58"; efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c"; efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0"; efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0"; zynqmp_pcap = "/firmware/zynqmp-firmware/pcap"; xlnx_aes = "/firmware/zynqmp-firmware/zynqmp-aes"; zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller"; pinctrl0 = "/firmware/zynqmp-firmware/pinctrl"; xlnx_keccak_384 = "/firmware/zynqmp-firmware/sha384"; xlnx_rsa = "/firmware/zynqmp-firmware/zynqmp-rsa"; modepin_gpio = "/firmware/zynqmp-firmware/gpio"; zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller"; fpga_full = "/fpga-full"; amba = "/axi"; can0 = "/axi/can@ff060000"; can1 = "/axi/can@ff070000"; cci = "/axi/cci@fd6e0000"; fpd_dma_chan1 = "/axi/dma-controller@fd500000"; fpd_dma_chan2 = "/axi/dma-controller@fd510000"; fpd_dma_chan3 = "/axi/dma-controller@fd520000"; fpd_dma_chan4 = "/axi/dma-controller@fd530000"; fpd_dma_chan5 = "/axi/dma-controller@fd540000"; fpd_dma_chan6 = "/axi/dma-controller@fd550000"; fpd_dma_chan7 = "/axi/dma-controller@fd560000"; fpd_dma_chan8 = "/axi/dma-controller@fd570000"; gic = "/axi/interrupt-controller@f9010000"; gpu = "/axi/gpu@fd4b0000"; lpd_dma_chan1 = "/axi/dma-controller@ffa80000"; lpd_dma_chan2 = "/axi/dma-controller@ffa90000"; lpd_dma_chan3 = "/axi/dma-controller@ffaa0000"; lpd_dma_chan4 = "/axi/dma-controller@ffab0000"; lpd_dma_chan5 = "/axi/dma-controller@ffac0000"; lpd_dma_chan6 = "/axi/dma-controller@ffad0000"; lpd_dma_chan7 = "/axi/dma-controller@ffae0000"; lpd_dma_chan8 = "/axi/dma-controller@ffaf0000"; mc = "/axi/memory-controller@fd070000"; nand0 = "/axi/nand-controller@ff100000"; gem0 = "/axi/ethernet@ff0b0000"; gem1 = "/axi/ethernet@ff0c0000"; gem2 = "/axi/ethernet@ff0d0000"; gem3 = "/axi/ethernet@ff0e0000"; phyc = "/axi/ethernet@ff0e0000/ethernet-phy@c"; gpio = "/axi/gpio@ff0a0000"; i2c0 = "/axi/i2c@ff020000"; i2c1 = "/axi/i2c@ff030000"; ocm = "/axi/memory-controller@ff960000"; perf_monitor_ocm = "/axi/perf-monitor@ffa00000"; perf_monitor_ddr = "/axi/perf-monitor@fd0b0000"; perf_monitor_cci = "/axi/perf-monitor@fd490000"; perf_monitor_lpd = "/axi/perf-monitor@ffa10000"; pcie = "/axi/pcie@fd0e0000"; pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller"; qspi = "/axi/spi@ff0f0000"; flash0 = "/axi/spi@ff0f0000/flash@0"; psgtr = "/axi/phy@fd400000"; rtc = "/axi/rtc@ffa60000"; sata = "/axi/ahci@fd0c0000"; sdhci0 = "/axi/mmc@ff160000"; sdhci1 = "/axi/mmc@ff170000"; smmu = "/axi/smmu@fd800000"; spi0 = "/axi/spi@ff040000"; spi1 = "/axi/spi@ff050000"; ttc0 = "/axi/timer@ff110000"; ttc1 = "/axi/timer@ff120000"; ttc2 = "/axi/timer@ff130000"; ttc3 = "/axi/timer@ff140000"; uart0 = "/axi/serial@ff000000"; uart1 = "/axi/serial@ff010000"; usb0 = "/axi/usb0@ff9d0000"; dwc3_0 = "/axi/usb0@ff9d0000/usb@fe200000"; usb1 = "/axi/usb1@ff9e0000"; dwc3_1 = "/axi/usb1@ff9e0000/usb@fe300000"; watchdog0 = "/axi/watchdog@fd4d0000"; lpd_watchdog = "/axi/watchdog@ff150000"; xilinx_ams = "/axi/ams@ffa50000"; ams_ps = "/axi/ams@ffa50000/ams_ps@ffa50800"; ams_pl = "/axi/ams@ffa50000/ams_pl@ffa50c00"; zynqmp_dpdma = "/axi/dma-controller@fd4c0000"; zynqmp_dpaud_setting = "/axi/dp_aud@fd4ac000"; zynqmp_dpsub = "/axi/display@fd4a0000"; zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0"; zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0"; zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1"; zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card"; fclk0 = "/fclk0"; fclk1 = "/fclk1"; fclk2 = "/fclk2"; fclk3 = "/fclk3"; pss_ref_clk = "/pss_ref_clk"; video_clk = "/video_clk"; pss_alt_ref_clk = "/pss_alt_ref_clk"; gt_crx_ref_clk = "/gt_crx_ref_clk"; aux_ref_clk = "/aux_ref_clk"; dp_aclk = "/dp_aclk"; amba_pl = "/amba_pl@0"; axi_iic_0 = "/amba_pl@0/i2c@80090000"; imx274 = "/amba_pl@0/i2c@80090000/sensor@1a"; sensor_out = "/amba_pl@0/i2c@80090000/sensor@1a/port@0/endpoint"; axi_uartlite_0 = "/amba_pl@0/serial@80000000"; hier_dpu_DPUCZDX8G = "/amba_pl@0/dpuczdx8g@8f000000"; misc_clk_0 = "/amba_pl@0/misc_clk_0"; misc_clk_1 = "/amba_pl@0/misc_clk_1"; hier_hdmirx20_v_frmbuf_wr_0 = "/amba_pl@0/v_frmbuf_wr@80030000"; hier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000"; hdmirx_portshier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000/ports"; hdmirx_porthier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000/ports/port@0"; hdmirx_outhier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000/ports/port@0/endpoint"; misc_clk_2 = "/amba_pl@0/misc_clk_2"; misc_clk_3 = "/amba_pl@0/misc_clk_3"; hier_hdmirx20_vid_phy_controller_0 = "/amba_pl@0/vid_phy_controller@80020000"; vphy_lane0 = "/amba_pl@0/vid_phy_controller@80020000/vphy_lane@0"; vphy_lane1 = "/amba_pl@0/vid_phy_controller@80020000/vphy_lane@1"; vphy_lane2 = "/amba_pl@0/vid_phy_controller@80020000/vphy_lane@2"; misc_clk_4 = "/amba_pl@0/misc_clk_4"; hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000"; mipi_csi_portshier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports"; mipi_csi_port1hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@1"; mipi_csirx_outhier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@1/endpoint"; mipi_csi_port0hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@0"; mipi_csi_inhier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@0/endpoint"; misc_clk_5 = "/amba_pl@0/misc_clk_5"; hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000"; demosaic_portshier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports"; demosaic_port1hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@1"; demo_outhier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@1/endpoint"; demosaic_port0hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@0"; hier_mipi_rx0_v_demosaic_0hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@0/endpoint"; hier_mipi_rx0_v_frmbuf_wr_0 = "/amba_pl@0/v_frmbuf_wr@80060000"; hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000"; gamma_portshier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports"; gamma_port1hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@1"; gamma_outhier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@1/endpoint"; gamma_port0hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@0"; hier_mipi_rx0_v_gamma_lut_0hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@0/endpoint"; hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000"; csc_portshier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports"; csc_port1hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@1"; csc_outhier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@1/endpoint"; csc_port0hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@0"; hier_mipi_rx0_v_proc_ss_0hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@0/endpoint"; hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000"; scaler_portshier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports"; scaler_port1hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@1"; sca_outhier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@1/endpoint"; scaler_port0hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@0"; hier_mipi_rx0_v_proc_ss_1hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@0/endpoint"; vcap_portshier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/vcap_hier_hdmirx20_v_hdmi_rx_ss_0/ports"; vcap_porthier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/vcap_hier_hdmirx20_v_hdmi_rx_ss_0/ports/port@0"; hier_hdmirx20_v_frmbuf_wr_0hier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/vcap_hier_hdmirx20_v_hdmi_rx_ss_0/ports/port@0/endpoint"; vcap_portshier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/vcap_hier_mipi_rx0_v_proc_ss_1/ports"; vcap_porthier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/vcap_hier_mipi_rx0_v_proc_ss_1/ports/port@0"; hier_mipi_rx0_v_frmbuf_wr_0hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/vcap_hier_mipi_rx0_v_proc_ss_1/ports/port@0/endpoint"; vid_s_axi_clk = "/amba_pl@0/vid_s_axi_clk"; psgtr_ref_0_pcie = "/psgtr_ref_0"; psgtr_ref_1_sata = "/psgtr_ref_1"; psgtr_ref_2_usb3 = "/psgtr_ref_2"; psgtr_ref_3_dp = "/psgtr_ref_3"; druclk_ref = "/druclk"; }; }; 有問題嗎
07-11
void SCRN_Display_DW(void) { static u32 icnt = 0; SCRN_DATA_P pScrnData = SCRN_GetScrnDataPtr(); if (icnt == 500) // 2000ms { SCRN_EnterPageById(pScrnData, SCRN_GetPageByLang(pageId_idle)); if (SYS_GetPressUnitState()) { SCRN_SetAddrText(ADDR_TextPressUnit, "hPa"); SCRN_SetAddrFoucus(ADDR_IconUnitHPa, 1); } else { SCRN_SetAddrText(ADDR_TextPressUnit, "cmH2O"); SCRN_SetAddrFoucus(ADDR_IconUnitHPa, 0); } if (SYS_GetTempeUnitState()) { SCRN_SetAddrText(ADDR_TextTempeUnit, "F"); } else { SCRN_SetAddrText(ADDR_TextTempeUnit, "C"); } SCRN_SetBrightLevel(SYS_GetBrightLevelState() * 20); if (PARAM_GetRunState() && !SYS_GetTherapyState()) { SCRN_SetTherapyState(1); } } if (icnt == 0) { SCRN_ClearCurveData(); //SCRN_SetAddrTxtID(ADDR_TestText, TXT_ThisTime); } else if (icnt < 1400)//1408 { /* 2025.05.21 changed by Chaoqi, 0 -> 45 */ SCRN_AddCurveDoubleData(45, 345); } else if (icnt % 15 == 1 && icnt >= 1400) //60ms调用一次 { pScrnData->fCurvePress = pScrnData->fCurvePress * 0.2f + Vent_GetPrsPatient() * 0.8f; pScrnData->fCurveFlow = pScrnData->fCurveFlow * 0.6f + Vent_GetFlowVolume() * 0.4f; SCRN_FillCurveDoubleData(pScrnData->uCurveCount, (u16)(pScrnData->fCurvePress * 50 + 10.5f), (u16)(pScrnData->fCurveFlow * 4 + 300.5f)); if (++pScrnData->uCurveCount > 350) { /* 2025.05.21 changed by Chaoqi, 0 -> 45 */ pScrnData->uCurveCount = 44;//24.4.9 原来25,通气时重启后,出现前一段不刷新,改为0 ty } } if (icnt % 8 == 2) //32ms调用一次 { SCRN_RecvAndUnPack(); } if (icnt % 20 == 3) //80ms调用一次 { SCRN_GetTouchData(); SCRN_UpdatePageInfo(); } if (icnt % 25 == 7) //100ms { // chg by gt 240318 scrn_DispPressBar(); } if (icnt % 50 == 5) //200ms调用一次 { if (PAPRM_GetPapMode() == MODE_CPAP || PAPRM_GetPapMode() == MODE_APAP) { pScrnData->uRealTimeIpap = Get_FilteredSmpValue(SMP_SNS_Prs_Pat) * 1 + g_sVentRun.fCurrEpapSet * 9; if (pScrnData->uRealTimeIpap <= 40.0f) { pScrnData->uRealTimeIpap = 40.0f; } pScrnData->uRealTimeEpap = Get_FilteredSmpValue(SMP_SNS_Prs_Pat) * 1 + (g_sVentRun.fCurrEpapSet - s_sPapParam.Flex) * 9; if (pScrnData->uRealTimeEpap <= 40.0f) { pScrnData->uRealTimeEpap = 40.0f; } } else { pScrnData->uRealTimeIpap = Get_FilteredSmpValue(SMP_SNS_Prs_Pat) * 1 + g_sVentRun.fCurrIpapSet * 9; pScrnData->uRealTimeEpap = Get_FilteredSmpValue(SMP_SNS_Prs_Pat) * 1 + g_sVentRun.fCurrEpapSet * 9; } //2024.3.26 added by Tianyongchang 实时压力显示 pScrnData->uRealTimePress = Get_FilteredSmpValue(SMP_SNS_Prs_Pat) * 10; pScrnData->uRealTimeRR = Vent_GetRespiratoryRate(); pScrnData->uRealTimeVT = Vent_GetTidalVolumeExp(); pScrnData->uRealTimeMV = Vent_GetMinuteVentilation() * 10.0f + 0.5f; pScrnData->uRealTimeTI = Get_RespPara(PARA_TI) * 1000 + 0.5f; pScrnData->uRealTimeLeak = (Vent_GetExceExpLeak() * 10.0f + 0.5f) * 0.6f; pScrnData->uRealTimeIERate = Vent_GetInsExpRate(); pScrnData->uRealTimeHR = 0; g_sSysData.bSpO2SnsFlag = (Get_RespPara(PARA_SpO2) > 5.0f) ? 1 : 0; if (g_sSysData.bSpO2SnsFlag) { pScrnData->uRealTimeTI = Get_RespPara(PARA_SpO2) * 1000; pScrnData->uRealTimeHR = Get_RespPara(PARA_HR) * 10; } } else if (icnt % 25 == 11) // 100ms调用一次 { if (--pScrnData->iUpdateFlag <= 0) { pScrnData->iUpdateFlag = 5; // 1秒调用一次,用于纠错 scrn_UpdatePage(); // 页面数据刷新 } } else if (icnt % 125 == 7) // 500调用一次 { scrn_SetDispData_1(); // 频繁使用显示公共数据 if (pScrnData->uWarnIconAct&0x0001) { if (pScrnData->uWarnIconAct&0x8000) { SCRN_SetAddrFoucus(ADDR_IconWarnAct, 1); pScrnData->uWarnIconAct &= ~0x8000; } else { SCRN_SetAddrFoucus(ADDR_IconWarnAct, 0); pScrnData->uWarnIconAct |= 0x8000; } } else { SCRN_SetAddrFoucus(ADDR_IconWarnAct, 0); } } // add by gt 230908 for 节能模式 100ms调用一次 if (SYS_GetEcModeState() && icnt % 25 == 13) { if (pScrnData->uStandCount < 300) { SCRN_SetBrightLevel(SYS_GetBrightLevelState() * 20); } /* 2024.3.13 changed by Chaoqi * Change maxiunm time from 1 minute to 10 second. * 2025.08.19 10s to 12s */ // if (pScrnData->uStandCount == 60000) if (pScrnData->uStandCount == 12000) { SCRN_EnterPageById(pScrnData, PAGE_Download_CN); SCRN_SetBrightLevel(0); } } //add by gt 231030 for 医生模式自动退出,自动回到第一页面(待机或通气页面) if (pScrnData->uDoctorFlag && icnt % 25 == 17) { if (pScrnData->uStandCount == 1200000) // 20分钟退出医生模式 { SCRN_ModeKeyProc(pScrnData); } } if (icnt % 25 == 3) { // 100ms调用一次 if (pScrnData->uStandCount < 3600000) { pScrnData->uStandCount += 100; } } if (++icnt >= 4000000000) { icnt = 2000; } /* 2024.04.03 added by Chaoqi * Added function of long touch adjust parameter data. */ static u16 longtouch_timer = 0; static u16 RefreshTime = 500; if (touching_flag) { longtouch_timer++; if (longtouch_timer == RefreshTime && SCRN_CurPageId(pScrnData) == PAGE_DataAdj_CN) { longtouch_timer = 0; u16 tmpVal = 0; RefreshTime = 100; if (Get_LasttimeAdjustData() == 1) { tmpVal = pScrnData->sParam2 - PARAM_GetAidStep(pScrnData->sParam1); } else if (Get_LasttimeAdjustData() == 2) { tmpVal = pScrnData->sParam2 + PARAM_GetAidStep(pScrnData->sParam1); } pScrnData->sParam2 = PARAM_ValidLimit(pScrnData->sParam1, tmpVal); SCRN_DispDataAdjVal(pScrnData->sParam1, pScrnData->sParam2); } } else { RefreshTime = 500; longtouch_timer = 0; } }
最新发布
11-08
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