我所知道的EC====>Uart

本文介绍了UART(通用异步收发器)在固件(FW)调试中的重要作用,以及如何通过printf、puts、putchar等函数将字符输出到串口。通过分析u-boot中的printf和puts函数实现,揭示了字符如何经过处理后通过串口发送,涉及到串口的波特率、硬件接口和相关寄存器操作。
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我所知道的EC====>Uart

 

1. Introduction

 

     “没有输出之前调试是一门艺术,有了输出以后调试就是一门技术!”这句话准确的道出了调试程序时能够查看运行状况和环境信息的重要性;尤其在FW环境下debug手段非常有限,uart是几乎所有FW都会采用的debug方式。Uart全称是 Universal Asynchronous Receiver/Transmitter通用异步收发器(异步串行通信口)它包括了RS232RS485等接口和总线标准规范, 它作为一种低速通信协议广泛应用于通信领域。

 

2. Hardware Interface

 

   Uart spec定义了非常多的信号,但debug过程中通常只需要接三根信号RXTXGND就可以了,故常见串口debug线路如下图1所示:

 

 

串口读写数据时数据送往内部的fifo,如果fifo满了数据就会按照顺讯逐个bit送往总线。数据读写的时序和格式如下图2所示:

 

串口通信常见的波特率有192001152009600480024001200 Bps,波特率可以通过寄存器配置。

 

3. How to Implement

 

     前一段时间有同事问我一个问题:”为什么我们EC之中使用printfputs putchar这些函数输出字符,字符会送给串口呢?以前写的DOS下的程序是输出到终端的呀。,他的困惑不无道理,为什么呢?不要着急,让我来告诉你其中的奥秘。若干年以前,我曾经在arm9上面porttingbootloaderu-boot,u-boot也有一个串口debug的部分,所以我就碰巧大致翻了翻这部分的代码,关注过这个问题J.先来看看printf的实现吧,下述代码是u-boot 中的printf code

 

     void printf (const char *fmt, ...)

    {

            va_list args;

            uint i;

            char printbuffer[CFG_PBSIZE];

 

            va_start (args, fmt);

 

            /* For this to work, printbuffer must be larger than

             * anything we ever want to print.

             */

            i = vsprintf (printbuffer, fmt, args);

            va_end (args);

 

            /* Print the string */

            puts (printbuffer);

}

 

注意看红色部分的代码,printf先使用vsprintf处理输入的参数,并将处理后的结果存入printbuffer,随后调用puts输出。那么我们看一下vsprintf的实现吧,下面的代码是vsprintfcode

  

   int vsprintf(char *buf, const char *fmt, va_list args)

   {

            int len;

            unsigned long num;

            int i, base;

            char * str;

            const char *s;

 

            int flags;                       /* flags to number() */

 

            int field_width;  /* width of output field */

            int precision;                  /* min. # of digits for integers; max

                                                   number of chars for from string */

            int qualifier;                  /* 'h', 'l', or 'q' for integer fields */

 

            for (str=buf ; *fmt ; ++fmt) {

                        if (*fmt != '%') {

                                    *str++ = *fmt;

                                    continue;

                        }

 

                        /* process flags */

                        flags = 0;

                        repeat:

                                    ++fmt;               /* this also skips first '%' */

                                    switch (*fmt) {

                                                case '-': flags |= LEFT; goto repeat;

                                                case '+': flags |= PLUS; goto repeat;

                                                case ' ': flags |= SPACE; goto repeat;

                                                case '#': flags |= SPECIAL; goto repeat;

                                                case '0': flags |= ZEROPAD; goto repeat;

                                                }

 

                        /* get field width */

                        field_width = -1;

                        if (is_digit(*fmt))

                                    field_width = skip_atoi(&fmt);

                        else if (*fmt == '*') {

                                    ++fmt;

                                    /* it's the next argument */

                                    field_width = va_arg(args, int);

                                    if (field_width < 0) {

                                                field_width = -field_width;

                                                flags |= LEFT;

                                    }

                        }

 

                        /* get the precision */

                        precision = -1;

                        if (*fmt == '.') {

                                    ++fmt;

                                    if (is_digit(*fmt))

                                                precision = skip_atoi(&fmt);

                                    else if (*fmt == '*') {

                                                ++fmt;

                                                /* it's the next argument */

                                                precision = va_arg(args, int);

                                    }

                                    if (precision < 0)

                                                precision = 0;

                        }

 

                        /* get the conversion qualifier */

                        qualifier = -1;

                        if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' ||

                            *fmt == 'Z' || *fmt == 'z' || *fmt == 't' ||

                            *fmt == 'q' ) {

                                    qualifier = *fmt;

                                    if (qualifier == 'l' && *(fmt+1) == 'l') {

                                                qualifier = 'q';

                                                ++fmt;

                                    }

                                    ++fmt;

                        }

 

                        /* default base */

                        base = 10;

 

                        switch (*fmt) {

                        case 'c':

                                    if (!(flags & LEFT))

                                                while (--field_width > 0)

                                                            *str++ = ' ';

                                    *str++ = (unsigned char) va_arg(args, int);

                                    while (--field_width > 0)

                                                *str++ = ' ';

                                    continue;

 

                        case 's':

                                    s = va_arg(args, char *);

                                    if (!s)

                                                s = "<NULL>";

 

                                    len = strnlen(s, precision);

 

                                    if (!(flags & LEFT))

                                                while (len < field_width--)

                                                            *str++ = ' ';

                                    for (i = 0; i < len; ++i)

                                                *str++ = *s++;

                                    while (len < field_width--)

                                                *str++ = ' ';

                                    continue;

 

                        case 'p':

                                    if (field_width == -1) {

                                                field_width = 2*sizeof(void *);

                                                flags |= ZEROPAD;

                                    }

                                    str = number(str,

                                                (unsigned long) va_arg(args, void *), 16,

                                                field_width, precision, flags);

                                    continue;

 

 

                        case 'n':

                                    if (qualifier == 'l') {

                                                long * ip = va_arg(args, long *);

                                                *ip = (str - buf);

                                    } else {

                                                int * ip = va_arg(args, int *);

                                                *ip = (str - buf);

                                    }

                                    continue;

 

                        case '%':

                                    *str++ = '%';

                                    continue;

 

                        /* integer number formats - set up the flags and "break" */

                        case 'o':

                                    base = 8;

                                    break;

 

                        case 'X':

                                    flags |= LARGE;

                        case 'x':

                                    base = 16;

                                    break;

 

                        case 'd':

                        case 'i':

                                    flags |= SIGN;

                        case 'u':

                                    break;

 

                        default:

                                    *str++ = '%';

                                    if (*fmt)

                                                *str++ = *fmt;

                                    else

                                                --fmt;

                                    continue;

                        }

                        if (qualifier == 'l') {

                                    num = va_arg(args, unsigned long);

                        } else if (qualifier == 'Z' || qualifier == 'z') {

                                    num = va_arg(args, size_t);

                        } else if (qualifier == 't') {

                                    num = va_arg(args, ptrdiff_t);

                        } else if (qualifier == 'h') {

                                    num = (unsigned short) va_arg(args, int);

                                    if (flags & SIGN)

                                                num = (short) num;

                        } else if (flags & SIGN)

                                    num = va_arg(args, int);

                        else

                                    num = va_arg(args, unsigned int);

                        str = number(str, num, base, field_width, precision, flags);

            }

            *str = '/0';

            return str-buf;

}

 

上述代码大致的意思就是解析fmt字符串,并据此分析计算args,最后将结果写入buf之中,有兴趣可以自己单步debug玩一玩。下面我们来看一看puts的实现代码:

      

       void puts (const char *s)

     {

#ifdef CONFIG_SILENT_CONSOLE

            if (gd->flags & GD_FLG_SILENT)

                        return;

#endif

            if (gd->flags & GD_FLG_DEVINIT)

            {

                        /* Send to the standard output */

                        fputs (stdout, s);

            }

            else

            {

                        /* Send directly to the handler */

                        serial_puts (s);

            }

}

 

这段code一出问题就明了了J,puts函数会先检查GD_FLG_SILENT flag如置起就什么都不干直接返回,silent就是安静的意思嘛J,而后会看GD_FLG_DEVINIT flag如置起,那么输出到stdout(也就是通常所说的终端),否则就是红色部分的代码了,这里就是问题的关键,它会调用serial_puts输出到串口了,到serial_puts这里就已经很明了了,反正一不做二不休,我们一追到底看个明白(我参考的是s3c24x0code):

 

void serial_puts (const char *s)

{

            _serial_puts(s, UART_NR);

}

 

void _serial_puts(const char *s, const int dev_index)

{

            while (*s)

            {

                        _serial_putc (*s++, dev_index);

            }

}

 

/*

 * Output a single byte to the serial port.

 */

void _serial_putc (const char c, const int dev_index)

{

            S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);

#ifdef CONFIG_MODEM_SUPPORT

            if (be_quiet)

                        return;

#endif

 

            /* wait for room in the tx FIFO */

            while (!(uart->UTRSTAT & 0x2));

 

#ifdef CONFIG_HWFLOW

            /* Wait for CTS up */

            while(hwflow && !(uart->UMSTAT & 0x1))

                        ;

#endif

 

            uart->UTXH = c;

 

            /* If /n, also do /r */

            if (c == '/n')

                        serial_putc ('/r');

}

 

 

图穷匕见,秘密终于揭开,红色部分的code已经说明一切了最终是通过操纵s3c24x0 uart register将数据抛出去的。经这一追printfputsputchar都解决了看完上面的分析之后,大家应该不会再困惑了吧!

 

 

That’s all!

 

Peter

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/dts-v1/; / { compatible = "xlnx,zynqmp"; #address-cells = <0x2>; #size-cells = <0x2>; cpus { #address-cells = <0x1>; #size-cells = <0x0>; cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <0x1>; reg = <0x0>; cpu-idle-states = <0x2>; clocks = <0x3 0xa>; phandle = <0x3a>; }; cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <0x1>; cpu-idle-states = <0x2>; phandle = <0x3b>; }; cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <0x1>; cpu-idle-states = <0x2>; phandle = <0x3c>; }; cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <0x1>; cpu-idle-states = <0x2>; phandle = <0x3d>; }; idle-states { entry-method = "psci"; cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <0x12c>; exit-latency-us = <0x258>; min-residency-us = <0x2710>; phandle = <0x2>; }; }; }; opp-table-cpu { compatible = "operating-points-v2"; opp-shared; phandle = <0x1>; opp00 { opp-hz = <0x0 0x4f7704c9>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp01 { opp-hz = <0x0 0x27bb8264>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp02 { opp-hz = <0x0 0x1a7d0198>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp03 { opp-hz = <0x0 0x13ddc132>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; }; zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <0x4>; interrupts = <0x0 0x23 0x4>; xlnx,ipi-id = <0x0>; #address-cells = <0x2>; #size-cells = <0x2>; ranges; phandle = <0x3e>; mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20 0x0 0xff9905e0 0x0 0x20 0x0 0xff990e80 0x0 0x20 0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <0x1>; xlnx,ipi-id = <0x4>; phandle = <0x5>; }; }; dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; phandle = <0x3f>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <0x4>; interrupts = <0x0 0x8f 0x4 0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; phandle = <0xc>; zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <0x4>; interrupts = <0x0 0x23 0x4>; mboxes = <0x5 0x0 0x5 0x1>; mbox-names = "tx", "rx"; phandle = <0x40>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <0x1>; #size-cells = <0x1>; soc_revision@0 { reg = <0x0 0x4>; phandle = <0x41>; }; efuse_dna@c { reg = <0xc 0xc>; phandle = <0x42>; }; efuse_usr0@20 { reg = <0x20 0x4>; phandle = <0x43>; }; efuse_usr1@24 { reg = <0x24 0x4>; phandle = <0x44>; }; efuse_usr2@28 { reg = <0x28 0x4>; phandle = <0x45>; }; efuse_usr3@2c { reg = <0x2c 0x4>; phandle = <0x46>; }; efuse_usr4@30 { reg = <0x30 0x4>; phandle = <0x47>; }; efuse_usr5@34 { reg = <0x34 0x4>; phandle = <0x48>; }; efuse_usr6@38 { reg = <0x38 0x4>; phandle = <0x49>; }; efuse_usr7@3c { reg = <0x3c 0x4>; phandle = <0x4a>; }; efuse_miscusr@40 { reg = <0x40 0x4>; phandle = <0x4b>; }; efuse_chash@50 { reg = <0x50 0x4>; phandle = <0x4c>; }; efuse_pufmisc@54 { reg = <0x54 0x4>; phandle = <0x4d>; }; efuse_sec@58 { reg = <0x58 0x4>; phandle = <0x4e>; }; efuse_spkid@5c { reg = <0x5c 0x4>; phandle = <0x4f>; }; efuse_ppk0hash@a0 { reg = <0xa0 0x30>; phandle = <0x50>; }; efuse_ppk1hash@d0 { reg = <0xd0 0x30>; phandle = <0x51>; }; }; pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; clocks = <0x3 0x29>; phandle = <0xb>; }; zynqmp-aes { compatible = "xlnx,zynqmp-aes"; phandle = <0x52>; }; reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <0x1>; phandle = <0xe>; }; pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; phandle = <0x53>; }; sha384 { compatible = "xlnx,zynqmp-keccak-384"; phandle = <0x54>; }; zynqmp-rsa { compatible = "xlnx,zynqmp-rsa"; phandle = <0x55>; }; gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <0x2>; phandle = <0x16>; }; clock-controller { u-boot,dm-pre-reloc; #clock-cells = <0x1>; compatible = "xlnx,zynqmp-clk"; clocks = <0x6 0x7 0x8 0x9 0xa>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; phandle = <0x3>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <0x4>; interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga-full { compatible = "fpga-region"; fpga-mgr = <0xb>; #address-cells = <0x2>; #size-cells = <0x2>; ranges; phandle = <0x56>; }; axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <0x2>; #size-cells = <0x2>; ranges; phandle = <0x57>; can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0x0 0x17 0x4>; interrupt-parent = <0x4>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <0xc 0x2f>; clocks = <0x3 0x3f 0x3 0x1f>; phandle = <0x58>; }; can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "okay"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0x0 0x18 0x4>; interrupt-parent = <0x4>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <0xc 0x30>; clocks = <0x3 0x40 0x3 0x1f>; phandle = <0x59>; }; cci@fd6e0000 { compatible = "arm,cci-400"; status = "okay"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <0x1>; #size-cells = <0x1>; phandle = <0x5a>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4>; }; }; dma-controller@fd500000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7c 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14e8>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5b>; }; dma-controller@fd510000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7d 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14e9>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5c>; }; dma-controller@fd520000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7e 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ea>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5d>; }; dma-controller@fd530000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x7f 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14eb>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5e>; }; dma-controller@fd540000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x80 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ec>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x5f>; }; dma-controller@fd550000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x81 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ed>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x60>; }; dma-controller@fd560000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x82 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ee>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x61>; }; dma-controller@fd570000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x83 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x80>; iommus = <0xd 0x14ef>; power-domains = <0xc 0x2a>; #dma-cells = <0x1>; clocks = <0x3 0x13 0x3 0x1f>; phandle = <0x62>; }; interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <0x3>; reg = <0x0 0xf9010000 0x0 0x10000 0x0 0xf9020000 0x0 0x20000 0x0 0xf9040000 0x0 0x20000 0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <0x4>; interrupts = <0x1 0x9 0xf04>; num_cpus = <0x2>; num_interrupts = <0x60>; phandle = <0x4>; }; gpu@fd4b0000 { status = "okay"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <0x4>; interrupts = <0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <0xc 0x3a>; clocks = <0x3 0x18 0x3 0x19 0x3 0x1a>; xlnx,tz-nonsecure = <0x1>; phandle = <0x63>; }; dma-controller@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x4d 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x64>; }; dma-controller@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x4e 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x65>; }; dma-controller@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x4f 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x66>; }; dma-controller@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x50 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x67>; }; dma-controller@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x51 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x68>; }; dma-controller@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x52 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x69>; }; dma-controller@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x53 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x6a>; }; dma-controller@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0x54 0x4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <0x40>; power-domains = <0xc 0x2b>; #dma-cells = <0x1>; clocks = <0x3 0x44 0x3 0x1f>; phandle = <0x6b>; }; memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <0x4>; interrupts = <0x0 0x70 0x4>; phandle = <0x6c>; }; nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <0x4>; interrupts = <0x0 0xe 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x872>; power-domains = <0xc 0x2c>; clocks = <0x3 0x3c 0x3 0x1f>; phandle = <0x6d>; }; ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x874>; power-domains = <0xc 0x1d>; resets = <0xe 0x1d>; clocks = <0x3 0x1f 0x3 0x68 0x3 0x2d 0x3 0x31 0x3 0x2c>; phandle = <0x6e>; }; ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x3b 0x4 0x0 0x3b 0x4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x875>; power-domains = <0xc 0x1e>; resets = <0xe 0x1e>; clocks = <0x3 0x1f 0x3 0x69 0x3 0x2e 0x3 0x32 0x3 0x2c>; phandle = <0x6f>; }; ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x876>; power-domains = <0xc 0x1f>; resets = <0xe 0x1f>; clocks = <0x3 0x1f 0x3 0x6a 0x3 0x2f 0x3 0x33 0x3 0x2c>; phandle = <0x70>; }; ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x877>; power-domains = <0xc 0x20>; resets = <0xe 0x20>; clocks = <0x3 0x1f 0x3 0x6b 0x3 0x30 0x3 0x34 0x3 0x2c>; phy-mode = "rgmii-id"; xlnx,ptp-enet-clock = <0x0>; local-mac-address = [ff ff ff ff ff ff]; phy-handle = <0xf>; phandle = <0x71>; ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; phandle = <0xf>; }; }; gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <0x4>; interrupts = <0x0 0x10 0x4>; interrupt-controller; #interrupt-cells = <0x2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <0xc 0x2e>; clocks = <0x3 0x1f>; emio-gpio-width = <0x20>; gpio-mask-high = <0x0>; gpio-mask-low = <0x5600>; phandle = <0x1f>; }; i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x11 0x4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x25>; clocks = <0x3 0x3d>; clock-frequency = <0x61a80>; phandle = <0x72>; }; i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x12 0x4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x26>; clocks = <0x3 0x3e>; clock-frequency = <0x61a80>; phandle = <0x73>; }; memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <0x4>; interrupts = <0x0 0xa 0x4>; phandle = <0x74>; }; perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0x0 0x19 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x1>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x1>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0x8>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1f>; phandle = <0x75>; }; perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0x0 0x7b 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x6>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x0>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0xa>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1c>; phandle = <0x76>; }; perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0x0 0x7b 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x1>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x0>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0x8>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1c>; phandle = <0x77>; }; perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0x0 0x19 0x4>; interrupt-parent = <0x4>; xlnx,enable-profile = <0x0>; xlnx,enable-trace = <0x0>; xlnx,num-monitor-slots = <0x1>; xlnx,enable-event-count = <0x1>; xlnx,enable-event-log = <0x1>; xlnx,have-sampled-metric-cnt = <0x1>; xlnx,num-of-counters = <0x8>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x1>; clocks = <0x3 0x1f>; phandle = <0x78>; }; pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; msi-controller; device_type = "pci"; interrupt-parent = <0x4>; interrupts = <0x0 0x76 0x4 0x0 0x75 0x4 0x0 0x74 0x4 0x0 0x73 0x4 0x0 0x72 0x4>; interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <0x10>; reg = <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd480000 0x0 0x1000 0x80 0x0 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x2000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000 0x43000000 0x6 0x0 0x6 0x0 0x2 0x0>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x0 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 0x11 0x1 0x0 0x0 0x0 0x2 0x11 0x2 0x0 0x0 0x0 0x3 0x11 0x3 0x0 0x0 0x0 0x4 0x11 0x4>; iommus = <0xd 0x4d0>; power-domains = <0xc 0x3b>; clocks = <0x3 0x17>; phandle = <0x10>; legacy-interrupt-controller { interrupt-controller; #address-cells = <0x0>; #interrupt-cells = <0x1>; phandle = <0x11>; }; }; spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupts = <0x0 0xf 0x4>; interrupt-parent = <0x4>; num-cs = <0x1>; reg = <0x0 0xff0f0000 0x0 0x1000 0x0 0xc0000000 0x0 0x8000000>; #address-cells = <0x1>; #size-cells = <0x0>; iommus = <0xd 0x873>; power-domains = <0xc 0x2d>; clocks = <0x3 0x35 0x3 0x1f>; is-dual = <0x1>; spi-rx-bus-width = <0x4>; spi-tx-bus-width = <0x4>; phandle = <0x79>; flash@0 { spi-tx-bus-width = <0x4>; spi-rx-bus-width = <0x4>; compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; #address-cells = <0x1>; #size-cells = <0x1>; spi-max-frequency = <0x2faf080>; phandle = <0x7a>; partition@0 { label = "qspi-boot"; reg = <0x0 0x1e00000>; }; partition@1 { label = "qspi-bootenv"; reg = <0x1e00000 0x40000>; }; partition@2 { label = "qspi-kernel"; reg = <0x1e40000 0x2140000>; }; partition@3 { label = "qspi-bootscr"; reg = <0x3f80000 0x80000>; }; partition@0x00000000 { label = "boot"; reg = <0x0 0x1e00000>; }; partition@0x01000000 { label = "bootenv"; reg = <0x1e00000 0x40000>; }; partition@0x00140000 { label = "kernel"; reg = <0x1e40000 0x2140000>; }; partition@0x01240000 { label = "bootscr"; reg = <0x3f80000 0x80000>; }; }; }; phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "okay"; reg = <0x0 0xfd400000 0x0 0x40000 0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <0x4>; clocks = <0x12 0x13 0x14 0x15>; clock-names = "ref0", "ref1", "ref2", "ref3"; phandle = <0x1a>; }; rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <0x4>; interrupts = <0x0 0x1a 0x4 0x0 0x1b 0x4>; interrupt-names = "alarm", "sec"; calibration = <0x7fff>; phandle = <0x7b>; }; ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "okay"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <0x4>; interrupts = <0x0 0x85 0x4>; power-domains = <0xc 0x1c>; resets = <0xe 0x10>; clocks = <0x3 0x16>; xlnx,tz-nonsecure-sata0 = <0x0>; xlnx,tz-nonsecure-sata1 = <0x0>; phandle = <0x7c>; }; mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x30 0x4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0x0>; iommus = <0xd 0x870>; power-domains = <0xc 0x27>; #clock-cells = <0x1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <0xe 0x26>; clocks = <0x3 0x36 0x3 0x1f>; assigned-clocks = <0x3 0x36>; phandle = <0x7d>; }; mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x31 0x4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0x1>; iommus = <0xd 0x871>; power-domains = <0xc 0x28>; #clock-cells = <0x1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <0xe 0x27>; clocks = <0x3 0x37 0x3 0x1f>; assigned-clocks = <0x3 0x37>; clock-frequency = <0xb2cbcae>; xlnx,mio-bank = <0x1>; phandle = <0x7e>; }; smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <0x1>; status = "disabled"; #global-interrupts = <0x1>; interrupt-parent = <0x4>; interrupts = <0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4>; phandle = <0xd>; }; spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x13 0x4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x23>; clocks = <0x3 0x3a 0x3 0x1f>; is-decoded-cs = <0x0>; num-cs = <0x1>; phandle = <0x7f>; spidev@0x00 { compatible = "rohm,dh2228fv"; spi-max-frequency = <0xf4240>; reg = <0x0>; }; }; spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <0x4>; interrupts = <0x0 0x14 0x4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <0x1>; #size-cells = <0x0>; power-domains = <0xc 0x24>; clocks = <0x3 0x3b 0x3 0x1f>; phandle = <0x80>; }; timer@ff110000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x24 0x4 0x0 0x25 0x4 0x0 0x26 0x4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x18>; clocks = <0x3 0x1f>; phandle = <0x81>; }; timer@ff120000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x27 0x4 0x0 0x28 0x4 0x0 0x29 0x4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x19>; clocks = <0x3 0x1f>; phandle = <0x82>; }; timer@ff130000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x2a 0x4 0x0 0x2b 0x4 0x0 0x2c 0x4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x1a>; clocks = <0x3 0x1f>; phandle = <0x83>; }; timer@ff140000 { compatible = "cdns,ttc"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x2d 0x4 0x0 0x2e 0x4 0x0 0x2f 0x4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <0x20>; power-domains = <0xc 0x1b>; clocks = <0x3 0x1f>; phandle = <0x84>; }; serial@ff000000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x15 0x4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <0xc 0x21>; clocks = <0x3 0x38 0x3 0x1f>; cts-override; device_type = "serial"; port-number = <0x0>; phandle = <0x85>; }; serial@ff010000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x16 0x4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <0xc 0x22>; clocks = <0x3 0x39 0x3 0x1f>; cts-override; device_type = "serial"; port-number = <0x2>; phandle = <0x86>; }; usb0@ff9d0000 { #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <0xc 0x16>; resets = <0xe 0x3b 0xe 0x3d 0xe 0x3f>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <0x16 0x1 0x1>; ranges; clocks = <0x3 0x20 0x3 0x22>; assigned-clocks = <0x3 0x20 0x3 0x22>; xlnx,tz-nonsecure = <0x1>; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phandle = <0x87>; usb@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <0x4>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0x0 0x41 0x4 0x0 0x45 0x4 0x0 0x4b 0x4>; iommus = <0xd 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-reset-on-resume; snps,xhci-stream-quirk; clocks = <0x3 0x22>; phandle = <0x88>; }; }; usb1@ff9e0000 { #address-cells = <0x2>; #size-cells = <0x2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <0xc 0x17>; resets = <0xe 0x3c 0xe 0x3e 0xe 0x40>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; clocks = <0x3 0x21 0x3 0x22>; assigned-clocks = <0x3 0x21 0x3 0x22>; phandle = <0x89>; usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <0x4>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0x0 0x46 0x4 0x0 0x4a 0x4 0x0 0x4c 0x4>; iommus = <0xd 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-reset-on-resume; snps,xhci-stream-quirk; clocks = <0x3 0x22>; phandle = <0x8a>; }; }; watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x71 0x1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <0x3c>; reset-on-timeout; clocks = <0x3 0x4b>; phandle = <0x8b>; }; watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x34 0x1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <0xa>; clocks = <0x3 0x70>; phandle = <0x8c>; }; ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "okay"; interrupt-parent = <0x4>; interrupts = <0x0 0x38 0x4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <0x2>; #size-cells = <0x2>; #io-channel-cells = <0x1>; ranges; clocks = <0x3 0x46>; phandle = <0x8d>; ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "okay"; reg = <0x0 0xffa50800 0x0 0x400>; phandle = <0x8e>; }; ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "okay"; reg = <0x0 0xffa50c00 0x0 0x400>; phandle = <0x8f>; }; }; dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "okay"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0x0 0x7a 0x4>; interrupt-parent = <0x4>; clock-names = "axi_clk"; power-domains = <0xc 0x29>; dma-channels = <0x6>; iommus = <0xd 0xce4>; #dma-cells = <0x1>; clocks = <0x3 0x14>; assigned-clocks = <0x3 0x14>; phandle = <0x18>; }; dp_aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; phandle = <0x17>; }; display@fd4a0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "okay"; reg = <0x0 0xfd4a0000 0x0 0x1000 0x0 0xfd4aa000 0x0 0x1000 0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <0x17>; interrupts = <0x0 0x77 0x4>; interrupt-parent = <0x4>; iommus = <0xd 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <0xc 0x29>; resets = <0xe 0x3>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <0x18 0x0 0x18 0x1 0x18 0x2 0x18 0x3>; clocks = <0x19 0x3 0x11 0x3 0x10>; assigned-clocks = <0x3 0x12 0x3 0x11 0x3 0x10>; phy-names = "dp-phy0", "dp-phy1"; phys = <0x1a 0x1 0x6 0x0 0x3 0x1a 0x0 0x6 0x1 0x3>; xlnx,max-lanes = <0x2>; phandle = <0x90>; i2c-bus { }; zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; clocks = <0x3 0x11>; status = "okay"; phandle = <0x1d>; }; zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <0x18 0x4>; dma-names = "tx"; status = "okay"; phandle = <0x1b>; }; zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <0x18 0x5>; dma-names = "tx"; status = "okay"; phandle = <0x1c>; }; zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <0x1b 0x1c>; xlnx,dp-snd-codec = <0x1d>; status = "okay"; phandle = <0x91>; }; }; }; fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x47>; phandle = <0x92>; }; fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x48>; phandle = <0x93>; }; fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x49>; phandle = <0x94>; }; fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x3 0x4a>; phandle = <0x95>; }; pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x1fc9350>; phandle = <0x6>; }; video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x1fc9f08>; phandle = <0x7>; }; pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x0>; phandle = <0x8>; }; gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x66ff300>; phandle = <0xa>; }; aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x19bfcc0>; phandle = <0x9>; }; dp_aclk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x5f5e100>; clock-accuracy = <0x64>; phandle = <0x19>; }; amba_pl@0 { #address-cells = <0x2>; #size-cells = <0x2>; compatible = "simple-bus"; ranges; phandle = <0x96>; i2c@80090000 { #address-cells = <0x1>; #size-cells = <0x0>; clock-names = "s_axi_aclk"; clocks = <0x1e>; compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; interrupt-names = "iic2intc_irpt"; interrupt-parent = <0x4>; interrupts = <0x0 0x6e 0x4>; reg = <0x0 0x80090000 0x0 0x10000>; phandle = <0x97>; sensor@1a { compatible = "sony,imx274"; reg = <0x1a>; #address-cells = <0x1>; #size-cells = <0x0>; reset-gpios = <0x1f 0x5a 0x1>; phandle = <0x98>; port@0 { reg = <0x0>; endpoint { remote-endpoint = <0x20>; phandle = <0x2d>; }; }; }; }; serial@80000000 { clock-names = "s_axi_aclk"; clocks = <0x3 0x47>; compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a"; current-speed = <0x1c200>; device_type = "serial"; interrupt-names = "interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x68 0x1>; port-number = <0x1>; reg = <0x0 0x80000000 0x0 0x10000>; xlnx,baudrate = <0x1c200>; xlnx,data-bits = <0x8>; xlnx,odd-parity = <0x0>; xlnx,s-axi-aclk-freq-hz-d = "99.990005"; xlnx,use-parity = <0x0>; phandle = <0x99>; }; dpuczdx8g@8f000000 { clock-names = "s_axi_aclk", "dpu_2x_clk", "m_axi_dpu_aclk"; clocks = <0x3 0x47 0x21 0x22>; compatible = "xlnx,dpuczdx8g-4.1"; interrupt-names = "dpu0_interrupt", "sfm_interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x59 0x4 0x0 0x5c 0x4>; reg = <0x0 0x8f000000 0x0 0x1000000>; phandle = <0x9a>; }; misc_clk_0 { #clock-cells = <0x0>; clock-frequency = <0x26bd3898>; compatible = "fixed-clock"; phandle = <0x21>; }; misc_clk_1 { #clock-cells = <0x0>; clock-frequency = <0x135e9c4c>; compatible = "fixed-clock"; phandle = <0x22>; }; v_frmbuf_wr@80030000 { #dma-cells = <0x1>; clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2"; interrupt-names = "interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x6b 0x4>; reg = <0x0 0x80030000 0x0 0x10000>; reset-gpios = <0x1f 0x58 0x1>; xlnx,dma-addr-width = <0x20>; xlnx,dma-align = <0x10>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,pixels-per-clock = <0x2>; xlnx,s-axi-ctrl-addr-width = <0x7>; xlnx,s-axi-ctrl-data-width = <0x20>; xlnx,vid-formats = "bgr888", "uyvy", "vuy888", "yuyv", "y_u_v8"; xlnx,video-width = <0x8>; phandle = <0x36>; }; v_hdmi_rx_ss@80010000 { clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk"; clocks = <0x3 0x47 0x23 0x3 0x48 0x24 0x3 0x48>; compatible = "xlnx,v-hdmi-rx-ss-3.2", "xlnx,v-hdmi-rx-ss-3.1"; interrupt-names = "irq"; interrupt-parent = <0x4>; interrupts = <0x0 0x69 0x4>; phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2"; phys = <0x25 0x0 0x1 0x1 0x0 0x26 0x0 0x1 0x1 0x0 0x27 0x0 0x1 0x1 0x0>; reg = <0x0 0x80010000 0x0 0x10000>; xlnx,edid-ram-size = <0x100>; xlnx,input-pixels-per-clock = <0x2>; xlnx,max-bits-per-component = <0x8>; phandle = <0x9b>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0x9c>; port@0 { reg = <0x0>; xlnx,video-format = <0x0>; xlnx,video-width = <0xa>; phandle = <0x9d>; endpoint { remote-endpoint = <0x28>; phandle = <0x37>; }; }; }; }; misc_clk_2 { #clock-cells = <0x0>; clock-frequency = <0x8d9ee20>; compatible = "fixed-clock"; phandle = <0x23>; }; misc_clk_3 { #clock-cells = <0x0>; clock-frequency = <0x11b3dc40>; compatible = "fixed-clock"; phandle = <0x24>; }; vid_phy_controller@80020000 { clock-names = "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtsouthrefclk0_in", "gtsouthrefclk0_odiv2_in", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk", "dru-clk"; clocks = <0x29 0x29 0x29 0x29 0x23 0x3 0x47 0x3 0x47 0x3 0x47 0x2a>; compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1"; interrupt-names = "irq"; interrupt-parent = <0x4>; interrupts = <0x0 0x6a 0x4>; reg = <0x0 0x80020000 0x0 0x10000>; xlnx,hdmi-fast-switch = <0x1>; xlnx,input-pixels-per-clock = <0x2>; xlnx,nidru = <0x1>; xlnx,nidru-refclk-sel = <0x4>; xlnx,rx-no-of-channels = <0x3>; xlnx,rx-pll-selection = <0x0>; xlnx,rx-protocol = <0x1>; xlnx,rx-refclk-sel = <0x1>; xlnx,transceiver-type = <0x5>; xlnx,transceiver-width = <0x2>; xlnx,tx-buffer-bypass = <0x1>; xlnx,tx-no-of-channels = <0x3>; xlnx,tx-pll-selection = <0x6>; xlnx,tx-protocol = <0x3>; xlnx,tx-refclk-sel = <0x1>; xlnx,use-gt-ch4-hdmi = <0x0>; phandle = <0x9e>; vphy_lane@0 { #phy-cells = <0x4>; phandle = <0x25>; }; vphy_lane@1 { #phy-cells = <0x4>; phandle = <0x26>; }; vphy_lane@2 { #phy-cells = <0x4>; phandle = <0x27>; }; }; misc_clk_4 { #clock-cells = <0x0>; clock-frequency = <0x5f5e100>; compatible = "fixed-clock"; phandle = <0x29>; }; mipi_csi2_rx_subsystem@80040000 { clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk"; clocks = <0x3 0x47 0x2b 0x3 0x48>; compatible = "xlnx,mipi-csi2-rx-subsystem-5.0"; interrupt-names = "csirxss_csi_irq"; interrupt-parent = <0x4>; interrupts = <0x0 0x6c 0x4>; reg = <0x0 0x80040000 0x0 0x1000>; xlnx,axis-tdata-width = <0x20>; xlnx,csi-pxl-format = <0x2b>; xlnx,en-active-lanes; xlnx,max-lanes = <0x4>; xlnx,ppc = <0x2>; xlnx,vc = <0x4>; xlnx,vfb; phandle = <0x9f>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xa0>; port@1 { reg = <0x1>; xlnx,cfa-pattern = "rggb"; xlnx,video-format = <0xc>; xlnx,video-width = <0x8>; phandle = <0xa1>; endpoint { remote-endpoint = <0x2c>; phandle = <0x2f>; }; }; port@0 { reg = <0x0>; xlnx,cfa-pattern = "rggb"; xlnx,video-format = <0xc>; xlnx,video-width = <0x8>; phandle = <0xa2>; endpoint { data-lanes = <0x1 0x2 0x3 0x4>; remote-endpoint = <0x2d>; phandle = <0x20>; }; }; }; }; misc_clk_5 { #clock-cells = <0x0>; clock-frequency = <0xbeb73e0>; compatible = "fixed-clock"; phandle = <0x2b>; }; v_demosaic@80050000 { clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-demosaic-1.1", "xlnx,v-demosaic"; reg = <0x0 0x80050000 0x0 0x10000>; reset-gpios = <0x1f 0x55 0x1>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,s-axi-ctrl-addr-width = <0x6>; xlnx,s-axi-ctrl-data-width = <0x20>; phandle = <0xa3>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xa4>; port@1 { reg = <0x1>; xlnx,cfa-pattern = "rggb"; xlnx,video-width = <0x8>; phandle = <0xa5>; endpoint { remote-endpoint = <0x2e>; phandle = <0x31>; }; }; port@0 { reg = <0x0>; xlnx,cfa-pattern = "rggb"; xlnx,video-width = <0x8>; phandle = <0xa6>; endpoint { remote-endpoint = <0x2f>; phandle = <0x2c>; }; }; }; }; v_frmbuf_wr@80060000 { #dma-cells = <0x1>; clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-frmbuf-wr-2.4", "xlnx,axi-frmbuf-wr-v2.2"; interrupt-names = "interrupt"; interrupt-parent = <0x4>; interrupts = <0x0 0x6d 0x4>; reg = <0x0 0x80060000 0x0 0x10000>; reset-gpios = <0x1f 0x50 0x1>; xlnx,dma-addr-width = <0x20>; xlnx,dma-align = <0x10>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,pixels-per-clock = <0x2>; xlnx,s-axi-ctrl-addr-width = <0x7>; xlnx,s-axi-ctrl-data-width = <0x20>; xlnx,vid-formats = "bgr888", "uyvy", "y8", "yuyv"; xlnx,video-width = <0x8>; phandle = <0x38>; }; v_gamma_lut@80070000 { clock-names = "ap_clk"; clocks = <0x3 0x48>; compatible = "xlnx,v-gamma-lut-1.1", "xlnx,v-gamma-lut"; reg = <0x0 0x80070000 0x0 0x10000>; reset-gpios = <0x1f 0x56 0x1>; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,s-axi-ctrl-addr-width = <0xd>; xlnx,s-axi-ctrl-data-width = <0x20>; phandle = <0xa7>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xa8>; port@1 { reg = <0x1>; xlnx,video-width = <0x8>; phandle = <0xa9>; endpoint { remote-endpoint = <0x30>; phandle = <0x33>; }; }; port@0 { reg = <0x0>; xlnx,video-width = <0x8>; phandle = <0xaa>; endpoint { remote-endpoint = <0x31>; phandle = <0x2e>; }; }; }; }; v_proc_ss@80080000 { clock-names = "aclk"; clocks = <0x3 0x48>; compatible = "xlnx,v-vpss-csc"; reg = <0x0 0x80080000 0x0 0x10000>; reset-gpios = <0x1f 0x54 0x1>; xlnx,colorspace-support = <0x2>; xlnx,csc-enable-window = "false"; xlnx,max-height = <0x870>; xlnx,max-width = <0xf00>; xlnx,num-video-components = <0x3>; xlnx,samples-per-clk = <0x2>; xlnx,topology = <0x3>; xlnx,use-uram = <0x0>; xlnx,video-width = <0x8>; phandle = <0xab>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xac>; port@1 { reg = <0x1>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xad>; endpoint { remote-endpoint = <0x32>; phandle = <0x35>; }; }; port@0 { reg = <0x0>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xae>; endpoint { remote-endpoint = <0x33>; phandle = <0x30>; }; }; }; }; v_proc_ss@800c0000 { clock-names = "aclk_axis", "aclk_ctrl"; clocks = <0x3 0x48 0x3 0x48>; compatible = "xlnx,v-vpss-scaler-2.2"; reg = <0x0 0x800c0000 0x0 0x40000>; reset-gpios = <0x1f 0x52 0x1>; xlnx,colorspace-support = <0x1>; xlnx,csc-enable-window = "true"; xlnx,enable-csc = "true"; xlnx,h-scaler-phases = <0x40>; xlnx,h-scaler-taps = <0x8>; xlnx,max-height = <0x870>; xlnx,max-num-phases = <0x40>; xlnx,max-width = <0xf00>; xlnx,num-hori-taps = <0x8>; xlnx,num-vert-taps = <0x8>; xlnx,pix-per-clk = <0x2>; xlnx,samples-per-clk = <0x2>; xlnx,scaler-algorithm = <0x2>; xlnx,topology = <0x0>; xlnx,use-uram = <0x0>; xlnx,v-scaler-phases = <0x40>; xlnx,v-scaler-taps = <0x8>; xlnx,video-width = <0x8>; phandle = <0xaf>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xb0>; port@1 { reg = <0x1>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xb1>; endpoint { remote-endpoint = <0x34>; phandle = <0x39>; }; }; port@0 { reg = <0x0>; xlnx,video-format = <0x3>; xlnx,video-width = <0x8>; phandle = <0xb2>; endpoint { remote-endpoint = <0x35>; phandle = <0x32>; }; }; }; }; vcap_hier_hdmirx20_v_hdmi_rx_ss_0 { compatible = "xlnx,video"; dma-names = "port0"; dmas = <0x36 0x0>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xb3>; port@0 { direction = "input"; reg = <0x0>; phandle = <0xb4>; endpoint { remote-endpoint = <0x37>; phandle = <0x28>; }; }; }; }; vcap_hier_mipi_rx0_v_proc_ss_1 { compatible = "xlnx,video"; dma-names = "port0"; dmas = <0x38 0x0>; ports { #address-cells = <0x1>; #size-cells = <0x0>; phandle = <0xb5>; port@0 { direction = "input"; reg = <0x0>; phandle = <0xb6>; endpoint { remote-endpoint = <0x39>; phandle = <0x34>; }; }; }; }; vid_s_axi_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x5f5b9f0>; phandle = <0x1e>; }; }; chosen { bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; stdout-path = "serial0:115200n8"; }; aliases { ethernet0 = "/axi/ethernet@ff0e0000"; i2c0 = "/axi/i2c@ff020000"; i2c1 = "/axi/i2c@ff030000"; i2c2 = "/amba_pl@0/i2c@80090000"; serial0 = "/axi/serial@ff000000"; serial1 = "/axi/serial@ff010000"; serial2 = "/amba_pl@0/serial@80000000"; spi0 = "/axi/spi@ff0f0000"; spi1 = "/axi/spi@ff040000"; }; memory { device_type = "memory"; reg = <0x0 0x0 0x0 0x7ff00000 0x8 0x0 0x0 0x80000000>; }; psgtr_ref_0 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x5f5e100>; phandle = <0x12>; }; psgtr_ref_1 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x7735940>; phandle = <0x13>; }; psgtr_ref_2 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x18cba80>; phandle = <0x14>; }; psgtr_ref_3 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <0x19bfcc0>; phandle = <0x15>; }; druclk { #clock-cells = <0x0>; clock-frequency = <0x9502f90>; compatible = "fixed-clock"; phandle = <0x2a>; }; __symbols__ { cpu0 = "/cpus/cpu@0"; cpu1 = "/cpus/cpu@1"; cpu2 = "/cpus/cpu@2"; cpu3 = "/cpus/cpu@3"; CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0"; cpu_opp_table = "/opp-table-cpu"; zynqmp_ipi = "/zynqmp_ipi"; ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff990400"; dcc = "/dcc"; zynqmp_firmware = "/firmware/zynqmp-firmware"; zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power"; soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0"; efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c"; efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20"; efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24"; efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28"; efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c"; efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30"; efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34"; efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38"; efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c"; efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40"; efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50"; efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54"; efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58"; efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c"; efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0"; efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0"; zynqmp_pcap = "/firmware/zynqmp-firmware/pcap"; xlnx_aes = "/firmware/zynqmp-firmware/zynqmp-aes"; zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller"; pinctrl0 = "/firmware/zynqmp-firmware/pinctrl"; xlnx_keccak_384 = "/firmware/zynqmp-firmware/sha384"; xlnx_rsa = "/firmware/zynqmp-firmware/zynqmp-rsa"; modepin_gpio = "/firmware/zynqmp-firmware/gpio"; zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller"; fpga_full = "/fpga-full"; amba = "/axi"; can0 = "/axi/can@ff060000"; can1 = "/axi/can@ff070000"; cci = "/axi/cci@fd6e0000"; fpd_dma_chan1 = "/axi/dma-controller@fd500000"; fpd_dma_chan2 = "/axi/dma-controller@fd510000"; fpd_dma_chan3 = "/axi/dma-controller@fd520000"; fpd_dma_chan4 = "/axi/dma-controller@fd530000"; fpd_dma_chan5 = "/axi/dma-controller@fd540000"; fpd_dma_chan6 = "/axi/dma-controller@fd550000"; fpd_dma_chan7 = "/axi/dma-controller@fd560000"; fpd_dma_chan8 = "/axi/dma-controller@fd570000"; gic = "/axi/interrupt-controller@f9010000"; gpu = "/axi/gpu@fd4b0000"; lpd_dma_chan1 = "/axi/dma-controller@ffa80000"; lpd_dma_chan2 = "/axi/dma-controller@ffa90000"; lpd_dma_chan3 = "/axi/dma-controller@ffaa0000"; lpd_dma_chan4 = "/axi/dma-controller@ffab0000"; lpd_dma_chan5 = "/axi/dma-controller@ffac0000"; lpd_dma_chan6 = "/axi/dma-controller@ffad0000"; lpd_dma_chan7 = "/axi/dma-controller@ffae0000"; lpd_dma_chan8 = "/axi/dma-controller@ffaf0000"; mc = "/axi/memory-controller@fd070000"; nand0 = "/axi/nand-controller@ff100000"; gem0 = "/axi/ethernet@ff0b0000"; gem1 = "/axi/ethernet@ff0c0000"; gem2 = "/axi/ethernet@ff0d0000"; gem3 = "/axi/ethernet@ff0e0000"; phyc = "/axi/ethernet@ff0e0000/ethernet-phy@c"; gpio = "/axi/gpio@ff0a0000"; i2c0 = "/axi/i2c@ff020000"; i2c1 = "/axi/i2c@ff030000"; ocm = "/axi/memory-controller@ff960000"; perf_monitor_ocm = "/axi/perf-monitor@ffa00000"; perf_monitor_ddr = "/axi/perf-monitor@fd0b0000"; perf_monitor_cci = "/axi/perf-monitor@fd490000"; perf_monitor_lpd = "/axi/perf-monitor@ffa10000"; pcie = "/axi/pcie@fd0e0000"; pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller"; qspi = "/axi/spi@ff0f0000"; flash0 = "/axi/spi@ff0f0000/flash@0"; psgtr = "/axi/phy@fd400000"; rtc = "/axi/rtc@ffa60000"; sata = "/axi/ahci@fd0c0000"; sdhci0 = "/axi/mmc@ff160000"; sdhci1 = "/axi/mmc@ff170000"; smmu = "/axi/smmu@fd800000"; spi0 = "/axi/spi@ff040000"; spi1 = "/axi/spi@ff050000"; ttc0 = "/axi/timer@ff110000"; ttc1 = "/axi/timer@ff120000"; ttc2 = "/axi/timer@ff130000"; ttc3 = "/axi/timer@ff140000"; uart0 = "/axi/serial@ff000000"; uart1 = "/axi/serial@ff010000"; usb0 = "/axi/usb0@ff9d0000"; dwc3_0 = "/axi/usb0@ff9d0000/usb@fe200000"; usb1 = "/axi/usb1@ff9e0000"; dwc3_1 = "/axi/usb1@ff9e0000/usb@fe300000"; watchdog0 = "/axi/watchdog@fd4d0000"; lpd_watchdog = "/axi/watchdog@ff150000"; xilinx_ams = "/axi/ams@ffa50000"; ams_ps = "/axi/ams@ffa50000/ams_ps@ffa50800"; ams_pl = "/axi/ams@ffa50000/ams_pl@ffa50c00"; zynqmp_dpdma = "/axi/dma-controller@fd4c0000"; zynqmp_dpaud_setting = "/axi/dp_aud@fd4ac000"; zynqmp_dpsub = "/axi/display@fd4a0000"; zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0"; zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0"; zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1"; zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card"; fclk0 = "/fclk0"; fclk1 = "/fclk1"; fclk2 = "/fclk2"; fclk3 = "/fclk3"; pss_ref_clk = "/pss_ref_clk"; video_clk = "/video_clk"; pss_alt_ref_clk = "/pss_alt_ref_clk"; gt_crx_ref_clk = "/gt_crx_ref_clk"; aux_ref_clk = "/aux_ref_clk"; dp_aclk = "/dp_aclk"; amba_pl = "/amba_pl@0"; axi_iic_0 = "/amba_pl@0/i2c@80090000"; imx274 = "/amba_pl@0/i2c@80090000/sensor@1a"; sensor_out = "/amba_pl@0/i2c@80090000/sensor@1a/port@0/endpoint"; axi_uartlite_0 = "/amba_pl@0/serial@80000000"; hier_dpu_DPUCZDX8G = "/amba_pl@0/dpuczdx8g@8f000000"; misc_clk_0 = "/amba_pl@0/misc_clk_0"; misc_clk_1 = "/amba_pl@0/misc_clk_1"; hier_hdmirx20_v_frmbuf_wr_0 = "/amba_pl@0/v_frmbuf_wr@80030000"; hier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000"; hdmirx_portshier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000/ports"; hdmirx_porthier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000/ports/port@0"; hdmirx_outhier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/v_hdmi_rx_ss@80010000/ports/port@0/endpoint"; misc_clk_2 = "/amba_pl@0/misc_clk_2"; misc_clk_3 = "/amba_pl@0/misc_clk_3"; hier_hdmirx20_vid_phy_controller_0 = "/amba_pl@0/vid_phy_controller@80020000"; vphy_lane0 = "/amba_pl@0/vid_phy_controller@80020000/vphy_lane@0"; vphy_lane1 = "/amba_pl@0/vid_phy_controller@80020000/vphy_lane@1"; vphy_lane2 = "/amba_pl@0/vid_phy_controller@80020000/vphy_lane@2"; misc_clk_4 = "/amba_pl@0/misc_clk_4"; hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000"; mipi_csi_portshier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports"; mipi_csi_port1hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@1"; mipi_csirx_outhier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@1/endpoint"; mipi_csi_port0hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@0"; mipi_csi_inhier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/mipi_csi2_rx_subsystem@80040000/ports/port@0/endpoint"; misc_clk_5 = "/amba_pl@0/misc_clk_5"; hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000"; demosaic_portshier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports"; demosaic_port1hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@1"; demo_outhier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@1/endpoint"; demosaic_port0hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@0"; hier_mipi_rx0_v_demosaic_0hier_mipi_rx0_mipi_csi2_rx_subsyst_0 = "/amba_pl@0/v_demosaic@80050000/ports/port@0/endpoint"; hier_mipi_rx0_v_frmbuf_wr_0 = "/amba_pl@0/v_frmbuf_wr@80060000"; hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000"; gamma_portshier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports"; gamma_port1hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@1"; gamma_outhier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@1/endpoint"; gamma_port0hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@0"; hier_mipi_rx0_v_gamma_lut_0hier_mipi_rx0_v_demosaic_0 = "/amba_pl@0/v_gamma_lut@80070000/ports/port@0/endpoint"; hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000"; csc_portshier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports"; csc_port1hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@1"; csc_outhier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@1/endpoint"; csc_port0hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@0"; hier_mipi_rx0_v_proc_ss_0hier_mipi_rx0_v_gamma_lut_0 = "/amba_pl@0/v_proc_ss@80080000/ports/port@0/endpoint"; hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000"; scaler_portshier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports"; scaler_port1hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@1"; sca_outhier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@1/endpoint"; scaler_port0hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@0"; hier_mipi_rx0_v_proc_ss_1hier_mipi_rx0_v_proc_ss_0 = "/amba_pl@0/v_proc_ss@800c0000/ports/port@0/endpoint"; vcap_portshier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/vcap_hier_hdmirx20_v_hdmi_rx_ss_0/ports"; vcap_porthier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/vcap_hier_hdmirx20_v_hdmi_rx_ss_0/ports/port@0"; hier_hdmirx20_v_frmbuf_wr_0hier_hdmirx20_v_hdmi_rx_ss_0 = "/amba_pl@0/vcap_hier_hdmirx20_v_hdmi_rx_ss_0/ports/port@0/endpoint"; vcap_portshier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/vcap_hier_mipi_rx0_v_proc_ss_1/ports"; vcap_porthier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/vcap_hier_mipi_rx0_v_proc_ss_1/ports/port@0"; hier_mipi_rx0_v_frmbuf_wr_0hier_mipi_rx0_v_proc_ss_1 = "/amba_pl@0/vcap_hier_mipi_rx0_v_proc_ss_1/ports/port@0/endpoint"; vid_s_axi_clk = "/amba_pl@0/vid_s_axi_clk"; psgtr_ref_0_pcie = "/psgtr_ref_0"; psgtr_ref_1_sata = "/psgtr_ref_1"; psgtr_ref_2_usb3 = "/psgtr_ref_2"; psgtr_ref_3_dp = "/psgtr_ref_3"; druclk_ref = "/druclk"; }; }; 有問題嗎
07-11
#include "stm32h7xx_hal.h" #include "usart.h" #include "usart7.h" #include "CRC16.h" #include "delay.h" #include "timer123.h" #include <string.h> #include <stdio.h> #include <stdarg.h> // 全局变量定义 UART_HandleTypeDef UartHandle; uint8_t ucTemp; extern uint8_t Rxflag; uart1_def rschuanko_1; uint16_t byte_tmp[2]; uint8_t huichuan_buff[]={0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00, 0x00 }; // 4G模块相关变量 int qi_ti_in[10]={0x00}; uint16_t zhuanhuan; uint8_t a=0; uint8_t ucTemp8; UART_HandleTypeDef UartHandle8; uart8_def rschuanko_8; uint16_t byte_tmp8[2]; extern uint8_t Rxflag8; uint8_t usRxCount8; uint8_t ucaRxBuf8[13]; uint8_t chuanko8jiesho[2]; // 4G模块控制定义 #define EC20_UART &UartHandle8 // EC20模块使用UART8通信 #define DEBUG_UART EC20_UART // 调试信息也使用UART8 #define APN "CMIOT" // 物联网卡APN #define MQTT_BROKER "tcp://118.190.157.186:61613" // MQTT服务器地址 #define MQTT_TOPIC "A/XZRS/0/1705001" // MQTT主题 #define MQTT_USER "system" // MQTT用户名 #define MQTT_PWD "jsjc@2025" // MQTT密码 // 数据上报JSON模板 const char *mqtt_payload = "{\n" "sensorDatas:\n" " [\n" " { sensorsId: 141705001,value:'1111'},\n" " ]\n" "}\n"; // 函数声明 void DEBUG_USART_Config(void); // 串口1配置函数 void USART1_IRQHandler(void); void rschuanko_1_uart1_tx(void); void rschuanko1_uart1_rx_timer_handle(void); void rschuanko_1_uart1_rx_handle(void); void DEBUG_USART_Config8(void); void UART8_IRQHandler(void); void rschuanko8_uart8_rx_timer_handle(void); void EC20_SendAT(const char *at_cmd, uint32_t timeout); uint8_t EC20_WaitResponse(const char *response, uint32_t timeout); void EC20_Init(void); void MQTT_Connect(void); void MQTT_Publish(const char *topic, const char *payload); void Debug_Print(const char *fmt, ...); void Print_MQTT_Content(const char *content, const char *label); // 串口1配置 void DEBUG_USART_Config(void) { GPIO_InitTypeDef GPIO_InitStruct; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; DEBUG_USART_RX_GPIO_CLK_ENABLE(); DEBUG_USART_TX_GPIO_CLK_ENABLE(); /* 配置串口1时钟源*/ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; RCC_PeriphClkInit.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit); /* 使能串口1时钟 */ DEBUG_USART_CLK_ENABLE(); /* 配置Tx引脚为复用功能 */ GPIO_InitStruct.Pin = DEBUG_USART_TX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Alternate = DEBUG_USART_TX_AF; HAL_GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStruct); /* 配置Rx引脚为复用功能 */ GPIO_InitStruct.Pin = DEBUG_USART_RX_PIN; GPIO_InitStruct.Alternate = DEBUG_USART_RX_AF; HAL_GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStruct); /* 配置串口1模式 */ UartHandle.Instance = DEBUG_USART; UartHandle.Init.BaudRate = 9600; UartHandle.Init.WordLength = UART_WORDLENGTH_8B; UartHandle.Init.StopBits = UART_STOPBITS_1; UartHandle.Init.Parity = UART_PARITY_NONE; UartHandle.Init.Mode = UART_MODE_TX_RX; UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; UartHandle.Init.OneBitSampling = UART_ONEBIT_SAMPLING_DISABLED; UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; if (HAL_UART_Init(&UartHandle) != HAL_OK) { while (1) {} } HAL_UART_Receive_IT(&UartHandle,&ucTemp,1); /*串口1中断初始化 */ HAL_NVIC_SetPriority(DEBUG_USART_IRQ, 2, 1); HAL_NVIC_EnableIRQ(DEBUG_USART_IRQ); } // UART8配置 void DEBUG_USART_Config8(void) { GPIO_InitTypeDef GPIO_InitStruct; __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_UART8_CLK_ENABLE(); // TX引脚配置 PE1 GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Alternate = GPIO_AF8_UART8; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); // RX引脚配置 PE0 GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Alternate = GPIO_AF8_UART8; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); // UART参数配置 UartHandle8.Instance = UART8; UartHandle8.Init.BaudRate = 9600; UartHandle8.Init.WordLength = UART_WORDLENGTH_8B; UartHandle8.Init.StopBits = UART_STOPBITS_1; UartHandle8.Init.Parity = UART_PARITY_NONE; UartHandle8.Init.Mode = UART_MODE_TX_RX; UartHandle8.Init.HwFlowCtl = UART_HWCONTROL_NONE; UartHandle8.Init.OverSampling = UART_OVERSAMPLING_16; UartHandle8.Init.OneBitSampling = UART_ONEBIT_SAMPLING_DISABLED; UartHandle8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; if (HAL_UART_Init(&UartHandle8) != HAL_OK) { while (1) {} } // 中断配置 HAL_UART_Receive_IT(&UartHandle8, &ucTemp8, 1); HAL_NVIC_SetPriority(UART8_IRQn, 4, 1); HAL_NVIC_EnableIRQ(UART8_IRQn); } // 串口1中断服务函数 void USART1_IRQHandler(void) { HAL_UART_IRQHandler(&UartHandle); } // UART8中断服务函数 void UART8_IRQHandler(void) { HAL_UART_IRQHandler(&UartHandle8); } // 串口接收回调函数 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { if(huart->Instance == DEBUG_USART) // 串口1 { rschuanko_1_uart1_tx(); } else if(huart->Instance == UART8) // UART8 { rschuanko_8.rx8_data[rschuanko_8.rx8_num++] = ucTemp8; rschuanko_8.rx8_delay = 30; if(rschuanko_8.rx8_num >= sizeof(rschuanko_8.rx8_data)) rschuanko_8.rx8_num = 0; HAL_UART_Receive_IT(&UartHandle8, &ucTemp8, 1); } } // 串口1数据处理函数 void rschuanko_1_uart1_tx(void) { if(rschuanko_1.rx_complete_flag==0) { if(rschuanko_1.rx_num<15) { rschuanko_1.rx_data[rschuanko_1.rx_num] = ucTemp; rschuanko_1.rx_num++; rschuanko_1.rx_delay = 20; } else { rschuanko_1.rx_complete_flag=1; } } HAL_UART_Receive_IT(&UartHandle,&ucTemp,1); } // 串口1接收逻辑处理函数 void rschuanko_1_uart1_rx_handle(void) { if(rschuanko_1.rx_complete_flag) { if(rschuanko_1.rx_num ==15) { byte_tmp[0]=CRC16_Get((uint8_t *)rschuanko_1.rx_data,13); byte_tmp[0]=byte_tmp[0]+0x31; if((rschuanko_1.rx_data[14]==(byte_tmp[0]>>8))&&(rschuanko_1.rx_data[13]==(byte_tmp[0]&0x00ff))) { memcpy(rschuanko_1.tx_data, (uint8_t*)rschuanko_1.rx_data, 13); buff[5]=1; } } rschuanko_1.rx_complete_flag=0; rschuanko_1.rx_num=0; rschuanko_1.rx_delay =0; } } // 串口1定时器处理函数(10ms周期) void rschuanko1_uart1_rx_timer_handle(void) { if(rschuanko_1.rx_delay) { rschuanko_1.rx_delay--; if(rschuanko_1.rx_delay==0) { rschuanko_1.rx_complete_flag=1; } } } // UART8定时器处理函数(10ms周期) void rschuanko8_uart8_rx_timer_handle(void) { if(rschuanko_8.rx8_delay) { rschuanko_8.rx8_delay--; if(rschuanko_8.rx8_delay == 0) rschuanko_8.rx8_complete_flag = 1; } } // MQTT内容打印函数(带格式标签) void Print_MQTT_Content(const char *content, const char *label) { // 使用相同串口打印标签和内容 char header[64]; snprintf(header, sizeof(header), "\r\n=== [%s] ===\r\n", label); HAL_UART_Transmit(DEBUG_UART, (uint8_t*)header, strlen(header), HAL_MAX_DELAY); // 打印内容(与MQTT_Publish使用相同串口) HAL_UART_Transmit(DEBUG_UART, (uint8_t*)content, strlen(content), HAL_MAX_DELAY); // 打印结束标记 const char *footer = "\r\n=== [END] ===\r\n"; HAL_UART_Transmit(DEBUG_UART, (uint8_t*)footer, strlen(footer), HAL_MAX_DELAY); } // 调试信息打印函数(使用与MQTT相同的串口) void Debug_Print(const char *fmt, ...) { static char buf[128]; // 使用静态缓冲区 va_list args; va_start(args, fmt); // 安全格式化字符串 int len = vsnprintf(buf, sizeof(buf) - 2, fmt, args); // 保留2字节给换行符 va_end(args); // 添加换行符 if (len > 0) { if (buf[len-1] != '\n') { buf[len++] = '\r'; buf[len++] = '\n'; buf[len] = '\0'; } } // 确保串口已初始化 // 添加调试信息标签 const char *prefix = "[DEBUG] "; HAL_UART_Transmit(DEBUG_UART, (uint8_t*)prefix, strlen(prefix), HAL_MAX_DELAY); // 使用阻塞模式发送 HAL_UART_Transmit(DEBUG_UART, (uint8_t*)buf, len, HAL_MAX_DELAY); } // 发送AT指令 void EC20_SendAT(const char *at_cmd, uint32_t timeout) { // 打印发送的指令内容(带标签) Print_MQTT_Content(at_cmd, "AT COMMAND SENT"); // 实际发送指令到模块 HAL_UART_Transmit(EC20_UART, (uint8_t*)at_cmd, strlen(at_cmd), timeout); } // 等待EC20响应 uint8_t EC20_WaitResponse(const char *response, uint32_t timeout) { uint32_t tickstart = HAL_GetTick(); while((HAL_GetTick() - tickstart) < timeout) { if(rschuanko_8.rx8_complete_flag) { rschuanko_8.rx8_data[rschuanko_8.rx8_num] = '\0'; // 打印模块响应(带标签) Print_MQTT_Content((char*)rschuanko_8.rx8_data, "MODULE RESPONSE"); if(strstr((char*)rschuanko_8.rx8_data, response) != NULL) { memset(rschuanko_8.rx8_data, 0, sizeof(rschuanko_8.rx8_data)); rschuanko_8.rx8_num = 0; rschuanko_8.rx8_complete_flag = 0; return 1; } memset(rschuanko_8.rx8_data, 0, sizeof(rschuanko_8.rx8_data)); rschuanko_8.rx8_num = 0; rschuanko_8.rx8_complete_flag = 0; } } return 0; } // EC20模块初始化 void EC20_Init(void) { Debug_Print("开始初始化EC20模块..."); // 添加延时确保模块就绪 HAL_Delay(500); EC20_SendAT("AT\r\n", 1000); if(!EC20_WaitResponse("OK", 2000)) { Debug_Print("模块未响应AT指令!"); return; } char apn_cmd[32]; sprintf(apn_cmd, "AT+CGDCONT=1,\"IP\",\"%s\"\r\n", APN); EC20_SendAT(apn_cmd, 1000); if(!EC20_WaitResponse("OK", 2000)) { Debug_Print("设置APN失败!"); return; } EC20_SendAT("AT+CGACT=1,1\r\n", 1000); if(!EC20_WaitResponse("OK", 5000)) { Debug_Print("激活PDP失败!"); return; } EC20_SendAT("AT+CREG?\r\n", 1000); if(EC20_WaitResponse("0,1", 2000) || EC20_WaitResponse("0,5", 2000)) { Debug_Print("网络注册成功!"); } else { Debug_Print("网络注册失败!"); return; } Debug_Print("EC20模块初始化完成!"); } // MQTT连接配置 void MQTT_Connect(void) { Debug_Print("开始连接MQTT服务器..."); char mqtt_server[64]; sprintf(mqtt_server, "AT+QMTCFG=\"broker\",0,\"%s\"\r\n", MQTT_BROKER); EC20_SendAT(mqtt_server, 1000); if(!EC20_WaitResponse("OK", 3000)) { Debug_Print("设置MQTT服务器失败!"); return; } char mqtt_auth[64]; sprintf(mqtt_auth, "AT+QMTCFG=\"auth\",0,\"%s\",\"%s\"\r\n", MQTT_USER, MQTT_PWD); EC20_SendAT(mqtt_auth, 1000); if(!EC20_WaitResponse("OK", 3000)) { Debug_Print("设置MQTT认证失败!"); return; } EC20_SendAT("AT+QMTOPEN=0\r\n", 1000); if(!EC20_WaitResponse("+QMTOPEN: 0,0", 10000)) { Debug_Print("MQTT连接失败!"); return; } EC20_SendAT("AT+QMTCONN=0,\"STM32_EC20_Client\"\r\n", 1000); if(!EC20_WaitResponse("+QMTCONN: 0,0,0", 5000)) { Debug_Print("MQTT客户端连接失败!"); return; } Debug_Print("MQTT服务器连接成功!"); } // MQTT发布消息(带调试信息显示) void MQTT_Publish(const char *topic, const char *payload) { // 打印主题信息(带标签) Print_MQTT_Content(topic, "MQTT TOPIC"); // 打印有效载荷(带标签) Print_MQTT_Content(payload, "MQTT PAYLOAD"); Debug_Print("发布MQTT消息..."); char publish_cmd[128]; sprintf(publish_cmd, "AT+QMTPUB=0,0,0,%d,\"%s\"\r\n", strlen(topic), topic); // 打印完整的AT指令 Print_MQTT_Content(publish_cmd, "PUBLISH COMMAND"); // 发送AT指令 EC20_SendAT(publish_cmd, 1000); if(EC20_WaitResponse(">", 2000)) { // 打印实际发送的有效载荷 Print_MQTT_Content(payload, "SENDING PAYLOAD"); // 发送有效载荷 HAL_UART_Transmit(EC20_UART, (uint8_t*)payload, strlen(payload), 5000); HAL_UART_Transmit(EC20_UART, (uint8_t*)"\x1A", 1, 1000); if(EC20_WaitResponse("+QMTPUB: 0,0,0", 5000)) { Debug_Print("MQTT消息发布成功!"); } else { Debug_Print("MQTT消息发布失败!"); } } } // 主函数 int main(void) { HAL_Init(); //初始化HAL库 Stm32_Clock_Init(); //设置时钟,400Mhz delay_init(400); //延时初始化 // 初始化UART8(EC20模块和调试共用) DEBUG_USART_Config8(); // 初始化串口1(可选,根据实际需要) DEBUG_USART_Config(); Debug_Print("系统启动,调试信息与MQTT内容使用同一串口(UART8)"); Debug_Print("波特率: 9600"); // 定时器初始化(10ms中断) timx_int_init123(50 - 1, 200- 1); // 初始化变量 memset(&rschuanko_1, 0, sizeof(rschuanko_1)); memset(&rschuanko_8, 0, sizeof(rschuanko_8)); // 添加延时确保系统稳定 HAL_Delay(10000); // EC20模块初始化 EC20_Init(); // 连接MQTT服务器 MQTT_Connect(); // 主循环 while(1) { // 处理串口1接收数据 rschuanko_1_uart1_rx_handle(); // 发布MQTT消息并显示内容 Debug_Print("准备发布MQTT消息..."); MQTT_Publish(MQTT_TOPIC, mqtt_payload); Debug_Print("等待10秒后再次发送..."); HAL_Delay(10000); } } 把这里面的串口8换成串口1,按照下面的格式配置//#include "usart.h" //#include "CRC16.h" //#include "timer123.h" ////图传 //UART_HandleTypeDef UartHandle; //uint8_t ucTemp; //extern uint8_t Rxflag; //uart1_def rschuanko_1; //uint16_t byte_tmp[2]; //uint8_t huichuan_buff[]={0x00,0x00,0x00,0x00,0x00, // 0x00,0x00,0x00,0x00,0x00, // 0x00,0x00,0x00,0x00,0x00, // 0x00,0x00,0x00,0x00,0x00, // 0x00,0x00,0x00,0x00,0x00, // 0x00 // }; // /** // * @brief DEBUG_USART GPIO 配置,工作模式配置。115200 8-N-1 // * @param 无 // * @retval 无 // */ //void DEBUG_USART_Config(void) //{ // GPIO_InitTypeDef GPIO_InitStruct; // RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; // // DEBUG_USART_RX_GPIO_CLK_ENABLE(); // DEBUG_USART_TX_GPIO_CLK_ENABLE(); // // /* 配置串口1时钟源*/ // RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; // RCC_PeriphClkInit.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; // HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit); // /* 使能串口1时钟 */ // DEBUG_USART_CLK_ENABLE(); // /* 配置Tx引脚为复用功能 */ // GPIO_InitStruct.Pin = DEBUG_USART_TX_PIN; // GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; // GPIO_InitStruct.Pull = GPIO_PULLUP; // GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // GPIO_InitStruct.Alternate = DEBUG_USART_TX_AF; // HAL_GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStruct); // // /* 配置Rx引脚为复用功能 */ // GPIO_InitStruct.Pin = DEBUG_USART_RX_PIN; // GPIO_InitStruct.Alternate = DEBUG_USART_RX_AF; // HAL_GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStruct); // // /* 配置串DEBUG_USART 模式 */ // UartHandle.Instance = DEBUG_USART; // UartHandle.Init.BaudRate = 115200; // UartHandle.Init.WordLength = UART_WORDLENGTH_8B; // UartHandle.Init.StopBits = UART_STOPBITS_1; // UartHandle.Init.Parity = UART_PARITY_NONE; // UartHandle.Init.Mode = UART_MODE_TX_RX; // UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; // UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; // UartHandle.Init.OneBitSampling = UART_ONEBIT_SAMPLING_DISABLED; // UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; // HAL_UART_Init(&UartHandle); //// HAL_UART_Receive_IT(&UartHandle, (uint8_t *)rschuanko_1.tx_data, rschuanko_1.rx_num); // HAL_UART_Receive_IT(&UartHandle,&ucTemp,1); // // // /*串口1中断初始化 */ //// __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_IDLE); // HAL_NVIC_SetPriority(DEBUG_USART_IRQ, 2, 1); // HAL_NVIC_EnableIRQ(DEBUG_USART_IRQ); // /*配置串口接收中断 */ // // // // // // //// __HAL_UART_ENABLE_IT(&UartHandle,UART_IT_RXNE); // //// __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_IDLE); //} ///***************** 发送字符串 **********************/ //void Usart_SendString(uint8_t *str) //{ // unsigned int k=0; // do // { // HAL_UART_Transmit( &UartHandle,(uint8_t *)(str + k) ,1,1000); // k++; // } while(*(str + k)!='\0'); // //} /////重定向c库函数printf到串口DEBUG_USART,重定向后可使用printf函数 //int fputc(int ch, FILE *f) //{ // /* 发送一个字节数据到串口DEBUG_USART */ // HAL_UART_Transmit(&UartHandle, (uint8_t *)&ch, 1, 1000); // // return (ch); //} ///////重定向c库函数scanf到串口DEBUG_USART,重写向后可使用scanf、getchar等函数 ////int fgetc(FILE *f) ////{ //// //// int ch; //// HAL_UART_Receive(&UartHandle, (uint8_t *)&ch, 1, 1000); //// return (ch); ////} ////void DEBUG_USART_IRQHandler(void) ////{ //// //// //// if(__HAL_UART_GET_IT( &UartHandle, UART_IT_RXNE ) != RESET) //// { //// //// HAL_UART_Receive(&UartHandle, (uint8_t *)&ucTemp, 1, 1000); //// ////// ////// if(rschuanko_1.rx_complete_flag==0) ////// { ////// if(rschuanko_1.rx_num<15) ////// { ////// rschuanko_1.rx_data[rschuanko_1.rx_num] = ucTemp; ////// rschuanko_1.rx_num++; ////// ////// //刷新延时 ////// rschuanko_1.rx_delay = 100; //超过50ms未收到数据及表示接收完毕 ////// } ////// else ////// { ////// rschuanko_1.rx_complete_flag=1; ////// } ////// } ////// ////// //// } ////// HAL_UART_Receive_IT(&UartHandle,&ucTemp,1); //// HAL_UART_IRQHandler(&UartHandle); ////} //void USART1_IRQHandler(void) //{ // /* USER CODE BEGIN USART6_IRQn 0 */ // /* USER CODE END USART6_IRQn 0 */ // HAL_UART_IRQHandler(&UartHandle); // /* USER CODE BEGIN USART6_IRQn 1 */ // /* USER CODE END USART6_IRQn 1 */ //} //void rschuanko_1_uart1_tx(void) //{ // // if(rschuanko_1.rx_complete_flag==0) // { // if(rschuanko_1.rx_num<15) // { // rschuanko_1.rx_data[rschuanko_1.rx_num] = ucTemp; // rschuanko_1.rx_num++; // // //刷新延时 // rschuanko_1.rx_delay = 20; //超过50ms未收到数据及表示接收完毕 // } // else // { // rschuanko_1.rx_complete_flag=1; // } // } // // HAL_UART_Receive_IT(&UartHandle,&ucTemp,1); //} ////逻辑处理函数 //void rschuanko_1_uart1_rx_handle(void) //{ // // // if(rschuanko_1.rx_complete_flag) // { // // if(rschuanko_1.rx_num ==15) // { // // byte_tmp[0]=CRC16_Get((uint8_t *)rschuanko_1.rx_data,13); // byte_tmp[0]=byte_tmp[0]+0x31; // if((rschuanko_1.rx_data[14]==(byte_tmp[0]>>8))&&(rschuanko_1.rx_data[13]==(byte_tmp[0]&0x00ff))) // { // rschuanko_1.tx_data[0]=rschuanko_1.rx_data[0]; // rschuanko_1.tx_data[1]=rschuanko_1.rx_data[1]; // rschuanko_1.tx_data[2]=rschuanko_1.rx_data[2]; // rschuanko_1.tx_data[3]=rschuanko_1.rx_data[3]; // rschuanko_1.tx_data[4]=rschuanko_1.rx_data[4]; // rschuanko_1.tx_data[5]=rschuanko_1.rx_data[5]; // rschuanko_1.tx_data[6]=rschuanko_1.rx_data[6]; // rschuanko_1.tx_data[7]=rschuanko_1.rx_data[7]; // rschuanko_1.tx_data[8]=rschuanko_1.rx_data[8]; // rschuanko_1.tx_data[9]=rschuanko_1.rx_data[9]; // rschuanko_1.tx_data[10]=rschuanko_1.rx_data[10]; // rschuanko_1.tx_data[11]=rschuanko_1.rx_data[11]; // rschuanko_1.tx_data[12]=rschuanko_1.rx_data[12]; //// HAL_UART_Transmit( &UartHandle, (uint8_t *)huichuan_buff,26,1000 ); // buff[5]=1; // } // // // // // } //// HAL_UART_Transmit( &UartHandle, (uint8_t *)huichuan_buff,26,1000 ); // //重新开始接收 // rschuanko_1.rx_complete_flag=0; // rschuanko_1.rx_num=0; // rschuanko_1.rx_delay =0; // // } //} ////定时器处理函数,定时器周期10ms //void rschuanko1_uart1_rx_timer_handle(void) //{ // if(rschuanko_1.rx_delay) // { // rschuanko_1.rx_delay--; // if(rschuanko_1.rx_delay==0) // { // rschuanko_1.rx_complete_flag=1; //接收完毕 // } // } //}
12-02
/* * Copyright (C) 2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include <dt-bindings/input/input.h> #include "imx6ull.dtsi" / { model = "Freescale i.MX6 ULL 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; chosen { stdout-path = &uart1; }; memory { reg = <0x80000000 0x20000000>; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; linux,cma { compatible = "shared-dma-pool"; reusable; size = <0x8000000>; linux,cma-default; }; }; backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; status = "okay"; }; pxp_v4l2 { compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; status = "okay"; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_can_3v3: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "can-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; reg_sd1_vmmc: regulator@1 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; /* gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; */ enable-active-high; }; reg_gpio_dvfs: regulator-gpio { compatible = "regulator-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dvfs>; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1400000>; regulator-name = "gpio_dvfs"; regulator-type = "voltage"; gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; states = <1300000 0x1 1400000 0x0>; }; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds &pinctrl_beep>; led1{ label = "sys-led"; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; default-state = "on"; }; beep{ label = "beep"; gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; gpio_keys: gpio_keys@0 { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; #address-cells = <1>; #size-cells = <0>; autorepeat; key1@1 { label = "USER-KEY1"; linux,code = <114>; gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; gpio-key,wakeup; }; }; sound { compatible = "fsl,imx6ul-evk-wm8960", "fsl,imx-audio-wm8960"; model = "wm8960-audio"; cpu-dai = <&sai2>; audio-codec = <&codec>; asrc-controller = <&asrc>; codec-master; gpr = <&gpr 4 0x100000 0x100000>; /* * hp-det = <hp-det-pin hp-det-polarity>; * hp-det-pin: JD1 JD2 or JD3 * hp-det-polarity = 0: hp detect high for headphone * hp-det-polarity = 1: hp detect high for speaker */ hp-det = <3 0>; /* hp-det-gpios = <&gpio5 4 0>; mic-det-gpios = <&gpio5 4 0>; */ audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", "Ext Spk", "SPK_RP", "Ext Spk", "SPK_RN", "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", "RINPUT1", "Main MIC", "RINPUT2", "Main MIC", "Mic Jack", "MICB", "Main MIC", "MICB", "CPU-Playback", "ASRC-Playback", "Playback", "CPU-Playback", "ASRC-Capture", "CPU-Capture", "CPU-Capture", "Capture"; }; spi4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; status = "disabled"; gpio-sck = <&gpio5 11 0>; gpio-mosi = <&gpio5 10 0>; cs-gpios = <&gpio5 7 0>; num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; gpio_spi: gpio_spi@0 { compatible = "fairchild,74hc595"; gpio-controller; #gpio-cells = <2>; reg = <0>; registers-number = <1>; registers-default = /bits/ 8 <0x57>; spi-max-frequency = <100000>; }; }; // ZXKnode:ZXK@0101{; sii902x_reset: sii902x-reset { compatible = "gpio-reset"; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; reset-delay-us = <100000>; #reset-cells = <0>; status = "disabled"; }; gpioled { #address-cells = <1>; #size-cells = <1>; compatible = "atkalpha-gpioled"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; led-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; }; &cpu0 { arm-supply = <&reg_arm>; soc-supply = <&reg_soc>; dc-supply = <&reg_gpio_dvfs>; }; &clks { assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <722534400>; }; &csi { status = "okay"; port { csi1_ep: endpoint { remote-endpoint = <&ov5640_ep>; }; }; }; &ecspi3 { fsl,spi-num-chipselects = <1>; cs-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; spidev: icm20608@0 { compatible = "alientek,icm20608"; spi-max-frequency = <8000000>; reg = <0>; }; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1 &pinctrl_fec1_reset>; phy-mode = "rmii"; phy-handle = <&ethphy0>; phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; phy-reset-duration = <200>; status = "okay"; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2 &pinctrl_fec2_reset>; phy-mode = "rmii"; phy-handle = <&ethphy1>; phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; phy-reset-duration = <200>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <&reg_can_3v3>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <&reg_can_3v3>; status = "disabled"; }; &gpc { fsl,cpu_pupscr_sw2iso = <0x1>; fsl,cpu_pupscr_sw = <0x0>; fsl,cpu_pdnscr_iso2sw = <0x1>; fsl,cpu_pdnscr_iso = <0x1>; fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ }; &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; mag3110@0e { compatible = "fsl,mag3110"; reg = <0x0e>; position = <2>; }; ap3216c@1e { compatible = "ap3216c"; reg = <0x1e>; }; }; &i2c2 { clock_frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; wlf,shared-lrclk; }; ov5640: ov5640@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi1 &csi_pwn_rst>; clocks = <&clks IMX6UL_CLK_CSI>; clock-names = "csi_mclk"; pwn-gpios = <&gpio1 4 1>; rst-gpios = <&gpio1 2 0>; csi_id = <0>; mclk = <24000000>; mclk_source = <0>; status = "okay"; port { ov5640_ep: endpoint { remote-endpoint = <&csi1_ep>; }; }; }; edt-ft5x06@38 { compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; pinctrl-names = "default"; pinctrl-0 = <&ts_int_pin &ts_reset_pin>; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 0>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; status = "okay"; }; goodix_ts@5d { compatible = "goodix,gt9xx"; reg = <0x5d>; status = "okay"; interrupt-parent = <&gpio1>; interrupts = <9 0>; pinctrl-0 = <&ts_int_pin &ts_reset_pin>; goodix,rst-gpio = <&gpio5 9 GPIO_ACTIVE_LOW>; goodix,irq-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; }; sii902x: sii902x@39 { compatible = "SiI,sii902x"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sii902x>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; mode_str = "1280x720M@60"; bits-per-pixel = <16>; resets = <&sii902x_reset>; reg = <0x39>; status = "disabled"; }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx6ul-evk { pinctrl_led: ledgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10B0 /* LED0 */ >; }; pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x13058 /* USB_OTG1_ID */ >; }; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b008 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b008 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b008 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b008 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b008 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b008 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b008 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b008 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b008 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b008 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b008 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b008 >; }; pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 >; }; pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 >; }; pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 /* MISO*/ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 /* MOSI*/ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 /* CLK*/ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x100b0 /* CS*/ >; }; pinctrl_gpio_leds: gpio-leds { fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 >; }; pinctrl_gpio_keys: gpio-keys { fsl,pins = < MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x80000000 >; }; pinctrl_flexcan1: flexcan1grp{ fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 >; }; pinctrl_flexcan2: flexcan2grp{ fsl,pins = < MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 >; }; pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x49 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x49 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x49 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x49 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x49 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x49 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x49 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x51 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x49 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x49 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x49 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x49 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x49 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x49 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x49 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x51 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x49 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x49 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x49 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x49 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x49 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x49 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x49 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x51 >; }; pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x49 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x49 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x49 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x49 >; }; pinctrl_pwm1: pwm1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 >; }; pinctrl_qspi: qspigrp { fsl,pins = < MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; }; pinctrl_sai2: sai2grp { fsl,pins = < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 >; }; pinctrl_sii902x: hdmigrp-1 { fsl,pins = < MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11 >; }; pinctrl_tsc: tscgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 >; }; pinctrl_uart2dte: uart2dtegrp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; }; pinctrl_usdhc2_8bit: usdhc2grp_8bit { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 >; }; pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 >; }; pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; ts_int_pin: ts_int_pin_mux { fsl,pins = < MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x49 >; }; csi_pwn_rst: csi_pwn_rstgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 >; }; }; }; &iomuxc_snvs { pinctrl-names = "default_snvs"; pinctrl-0 = <&pinctrl_hog_2>; imx6ul-evk { pinctrl_hog_2: hoggrp-2 { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 >; }; pinctrl_dvfs: dvfsgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 >; }; pinctrl_lcdif_reset: lcdifresetgrp { fsl,pins = < /* used for lcd reset */ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49 >; }; pinctrl_spi4: spi4grp { fsl,pins = < MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 >; }; pinctrl_fec1_reset: fec1_resetgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79 >; }; pinctrl_fec2_reset: fec2_resetgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x79 >; }; pinctrl_sai2_hp_det_b: sai2_hp_det_grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 >; }; ts_reset_pin: ts_reset_pin_mux { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49 >; }; pinctrl_beep: beep { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 >; }; }; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; display = <&display0>; status = "okay"; display0: display { bits-per-pixel = <16>; bus-width = <24>; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <35500000>; hactive = <800>; vactive = <480>; hfront-porch = <210>; hback-porch = <46>; hsync-len = <20>; vback-porch = <23>; vfront-porch = <22>; vsync-len = <3>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; /* rgb to hdmi: pixelclk-ative should be set to 1 */ pixelclk-active = <0>; }; }; }; }; &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pxp { status = "okay"; }; &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; ddrsmp=<0>; flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a"; spi-max-frequency = <29000000>; spi-nor,ddr-quad-read-dummy = <6>; reg = <0>; }; }; &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2 &pinctrl_sai2_hp_det_b>; assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, <&clks IMX6UL_CLK_SAI2>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <11289600>; status = "okay"; }; &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xfff>; status = "disabled"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; fsl,uart-has-rtscts; /* for DTE mode, add below change */ /* fsl,dte-mode; */ /* pinctrl-0 = <&pinctrl_uart2dte>; */ status = "disabled"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; &usbotg1 { dr_mode = "otg"; srp-disable; hnp-disable; adp-disable; status = "okay"; }; &usbotg2 { dr_mode = "host"; disable-over-current; status = "okay"; }; &usbphy1 { tx-d-cal = <0x5>; }; &usbphy2 { tx-d-cal = <0x5>; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; keep-power-in-suspend; enable-sdio-wakeup; vmmc-supply = <&reg_sd1_vmmc>; no-1-8-v; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; non-removable; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,wdog_b; }; 这是我设备树的代码
最新发布
12-05
<think>嗯,用户这次问的是EC20模块的AT指令具体用法,看起来是在做物联网数据传输相关的开发。从引用代码看,用户应该已经会基础的AT指令交互了,但需要更专业的周期性发送配置指导。 用户提供的函数Iot_SendCmd显示他们用UARTEC800模块通信,但问题却是问EC20。这里需要明确:虽然代码引用是EC800,但AT指令"AT+QICFG"确实是EC20系列专有的。用户可能是混淆了模块型号,也可能是项目同时用了不同模块。不过既然指令明确指向EC20,就按这个回答。 关于AT+QICFG="send/auto"指令,有几点关键信息需要传达: 第一要强调这是Quectel私有指令,标准AT手册可能不包含;第二要解释三个核心参数:开关、间隔时间、单次包长;第三要说明TCP/UDP模式下的区别。用户可能不知道周期性发送需要先建立socket连接,这个坑必须重点提醒。 注意到用户代码里用了CLEAR_EC800_Buffer这类操作,推断他们熟悉底层串口通信。在回复时可以适当深入,比如提到指令响应可能有"OK"和"ERROR"之外的中间状态码。但也要考虑用户可能在调试阶段,所以给出完整示例流程很重要——从建立连接、设置参数到关闭的完整链条。 用户上次问过AT指令超时处理(wait参数),这次代码里也有超时判断逻辑。虽然问题不直接相关,但在补充说明里加了超时建议,这样能延续之前的对话上下文。毕竟调试AT指令时,超时和异常处理总是痛点。 最后生成的问题要覆盖延伸场景:心跳机制替代方案是个实用方向,因为实际项目里经常要权衡内置功能与自定义实现;错误排查则针对调试刚需;模式切换问题则是考虑到用户之后可能要动态调整发送策略。这些应该都是用户后续会遇到的真实问题。 </think>EC20模块使用`AT+QICFG="send/auto"`指令设置周期性发送数据的方法如下: --- ### **指令功能说明** `AT+QICFG="send/auto"`是Quectel EC20专有指令,用于启用/禁用TCP/UDP连接的**自动周期性数据发送功能**。启用后,模块会按设定间隔自动向服务器发送指定长度的数据包,适用于心跳包维持连接等场景。 --- ### **指令语法** ```bash AT+QICFG="send/auto",<enable>,<interval>,<length> ``` #### **参数详解** | 参数 | 取值范围 | 说明 | |------------|----------------|----------------------------------------------------------------------| | `<enable>` | 0 或 1 | **0**: 关闭自动发送<br>**1**: 开启自动发送 | | `<interval>`| 1~65535 (单位:秒) | 发送间隔时间,例如 `60` 表示每分钟发送一次 | | `<length>` | 1~1460 (单位:字节) | 每次发送的数据包长度(自动填充空字节),建议不超过MTU值避免分片 | --- ### **配置步骤** 1. **开启自动发送模式** 启用60秒间隔、发送100字节空包的配置: ```bash AT+QICFG="send/auto",1,60,100 ``` **响应**: `+QICFG: "send/auto",1,60,100` `OK` 2. **关闭自动发送模式** ```bash AT+QICFG="send/auto",0 ``` **响应**: `+QICFG: "send/auto",0` `OK` --- ### **关键注意事项** 1. **依赖TCP/UDP连接** - 需先通过`AT+QIOPEN`建立有效连接(如TCP客户端)后方能生效。 - 若连接断开,自动发送自动停止。 2. **数据包内容** - 发送内容为**固定长度的空字节包**(由模块自动填充),不可自定义数据内容。 - 若需发送业务数据,需改用普通发送指令(如`AT+QISEND`)。 3. **资源消耗** 高频发送会增加模块功耗,电池供电场景需谨慎设置`<interval>`。 4. **模式优先级** 开启后,手动执行`AT+QISEND`会**临时中断自动发送周期**,下一次发送仍按间隔执行。 --- ### **完整流程示例** ```bash // 1. 激活PDP上下文 AT+QIACT=1 OK // 2. 建立TCP连接(示例服务器) AT+QIOPEN=1,0,"TCP","123.45.67.89",1234,0,0 OK +QIOPEN: 0,0 // 3. 启用自动发送:每30秒发送50字节空包 AT+QICFG="send/auto",1,30,50 +QICFG: "send/auto",1,30,50 OK // 4. 关闭自动发送(操作完成时) AT+QICFG="send/auto",0 +QICFG: "send/auto",0 OK ``` --- ### **常见问题排查** - **返回`ERROR`** 检查当前是否已建立有效连接,或尝试重启模块后重试。 - **服务器未收到数据** 确认防火墙是否拦截小数据包,或抓包验证链路状态。 - **参数不生效** 确保使用最新固件(旧版本可能不支持此指令)。 > 提示:实际应用时需结合业务需求权衡间隔时间与功耗,短间隔(<30秒)适用于强实时场景,长间隔(>300秒)利于节能[^1]。 ---
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