MMU相关指令学习（一）（主要是页表设置指令）

最新推荐文章于 2024-01-26 14:20:08 发布

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最新推荐文章于 2024-01-26 14:20:08 发布

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本文链接：https://blog.youkuaiyun.com/hfdghjh/article/details/87891634

本文深入探讨了MMU（内存管理单元）的作用及其在虚拟地址与物理地址转换过程中的关键角色。详细解析了ARM MMU的多层页表结构，包括L1和L2页表的工作原理，以及不同页表项的设置与功能。此外，文章对比了单步搜索与两步搜索在页表搜索中的应用，为理解复杂内存管理提供了清晰的视角。

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下面看看这张图，结合指令看看，不过我始终觉得这个图和程序描述的设置有很大差别。

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这里再来补充一下MMU的作用以及不使用MMU会造成什么后果。

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MMU把虚拟地址转换成物理地址；控制内存访问权限；决定内存页的写缓冲和cache。如果禁用MMU，虚拟地址会一一对应物理地址（相等）

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页表的结构

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ARM MMU是具有多层页表结构，分为两级页表：L1和L2。L1成为主页表，可以包含两种也表项：可以指向L2页表的起始地址和转换成1MB页的页表项。L1主页表也可以称为段页表。

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L1页表项设置

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A section page table entry points toa1MB section of memory. The upper 12 bits of
the page table entry replace the upper 12 bits of the virtual address to generate the physical
address. A section entry also contains the domain, cached, buffered, and access permission
attributes, which we discuss in Section 14.6.
A coarse page entry contains a pointer to the base address of a second-level coarse page
table. The coarse page table entry also contains domain information for the 1 MB section
of virtual memory represented by the L1 table entry. For coarse pages, the tables must be
aligned on an address multiple of 1 KB.
A ﬁne page table entry contains a pointer to the base address of a second-level ﬁne page
table. The ﬁne page table entry also contains domain information for the 1 MB section of
virtual memory represented by the L1 table entry. Fine page tables must be aligned on an
address multiple of 4 KB.
A fault page table entry generates a memory page fault. The fault condition results in
either a prefetch or data abort, depending on the type of memory access attempted.
The location of the L1 master page table in memory is set by writing to the CP15:c2
register.

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L1转换表基地址

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The CP15:c2 register holds the translation table base address (TTB)—an address pointing to the location of the master L1 table in virtual memory（指出L1页表在虚拟内存中的地址）. Figure 14.7 shows the format of CP15:c2 register.