ACM集训队作业(3)poj 1659

探讨了一种基于Havel定理的图构建方法,用于解决青蛙邻居问题,即根据每只青蛙的邻居数量确定湖泊间的连接关系。通过排序和减操作验证了给定的邻居数量是否能构成有效图。

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Frogs' Neighborhood

Time Limit: 5000MS Memory Limit: 10000K
Total Submissions: 11096 Accepted: 4647 Special Judge

Description

未名湖附近共有N个大小湖泊L1, L2, ..., Ln(其中包括未名湖),每个湖泊Li里住着一只青蛙Fi(1 ≤ i ≤ N)。如果湖泊LiLj之间有水路相连,则青蛙FiFj互称为邻居。现在已知每只青蛙的邻居数目x1, x2, ..., xn,请你给出每两个湖泊之间的相连关系。

Input

第一行是测试数据的组数T(0 ≤ T ≤ 20)。每组数据包括两行,第一行是整数N(2 < N < 10),第二行是N个整数,x1, x2,..., xn(0 ≤ xi ≤ N)。

Output

对输入的每组测试数据,如果不存在可能的相连关系,输出"NO"。否则输出"YES",并用N×N的矩阵表示湖泊间的相邻关系,即如果湖泊i与湖泊j之间有水路相连,则第i行的第j个数字为1,否则为0。每两个数字之间输出一个空格。如果存在多种可能,只需给出一种符合条件的情形。相邻两组测试数据之间输出一个空行。

Sample Input

3
7
4 3 1 5 4 2 1 
6
4 3 1 4 2 0 
6
2 3 1 1 2 1 

Sample Output

YES
0 1 0 1 1 0 1 
1 0 0 1 1 0 0 
0 0 0 1 0 0 0 
1 1 1 0 1 1 0 
1 1 0 1 0 1 0 
0 0 0 1 1 0 0 
1 0 0 0 0 0 0 

NO

YES
0 1 0 0 1 0 
1 0 0 1 1 0 
0 0 0 0 0 1 
0 1 0 0 0 0 
1 1 0 0 0 0 
0 0 1 0 0 0 

Source

POJ Monthly--2004.05.15 Alcyone@pku

周二晚上郑老师讲了一个关于造图的havel定理,就是不断地对给定的权值进行排序,知道出现负数或者全为0

出现负数说明不能构成图,全为0说明可以构成图。

gem大佬说,判断是否是图就可以用来构图,仔细想想很对。

不过提交的时候要注意本题的坑,每行测试数据要换行!!!wa了三次全是在换行上

#include<iostream>
#include<cstring>
#include<algorithm>
using namespace std;
int mapp[15][15];
struct node{
	int val;
	int idx;
};
bool cmp(node a,node b)
{
	return a.val>b.val;
}

bool Hami(node arr[],int cur,int n)
{
	sort(arr+cur,arr+n,cmp);
	if(arr[n-1].val<0)	return false;
	if(cur==n)	return true;
	int mm=arr[cur].val;
	cur+=1;
	for(int i=cur;i<=cur-1+mm;i++)
	{
		arr[i].val--;
		//cout<<arr[i]<<' ';
	}
	Hami(arr,cur,n);
}
int main()
{
	int T;
	cin>>T;
	node arr[15];
	node brr[15];
	bool flag;
	while(T--)
	{
		int N;
		cin>>N;
		memset(mapp,0,sizeof(mapp));
		for(int i=0;i<N;i++)
		{
			cin>>arr[i].val;
			arr[i].idx=i;
			brr[i].val=arr[i].val;
			brr[i].idx=arr[i].idx;
		}
		flag=Hami(arr,0,N);
		if(flag){
			cout<<"YES"<<endl;
			int cur=0;
			sort(brr+cur,brr+N,cmp);
			
			while(brr[cur].val!=0)
			{
				for(int i=cur+1;i<=cur+brr[cur].val;i++)
				{
					mapp[brr[i].idx][brr[cur].idx]=1;
					mapp[brr[cur].idx][brr[i].idx]=1;
					brr[i].val-=1;
				}
				cur++;
				sort(brr+cur,brr+N,cmp);
				
			}

			for(int i=0;i<N;i++)
			{
				for(int j=0;j<N;j++)
				{
					cout<<mapp[i][j]<<" ";
				}
				cout<<endl;
			}
			cout<<endl;
		}
		else{
			cout<<"NO"<<endl;
			cout<<endl;
			continue;
		}
	}
	return 0;
}

 

1.1 FEATURES  Memory configuration  Four 8-bit timer. (T0, TC0, TC1, TC2). Flash ROM size: 6K x 16 bits. Including EEROM T0: Basic timer. emulation. (In system programming) TC0: Timer/counter/PWM0. RAM size: 512 x 8 bits. TC1: Timer/counter/PWM1.  8 levels stack buffer. TC2: Timer/counter/PWM2  13 interrupt sources  3 channel duty/cycle programmable PWM to 11 internal interrupts: T0, TC0, TC1, TC2, T1, ADC, Generate PWM, Buzzer and IR carrier signals. SIO, MSP, UTX(UART TX), URX(UART RX), WAKE (PWM0~2). 2 external interrupts: INT0, INT1  One 16-bit timer (T1) with capture timer function  Multi-interrupt vector structure.  12- channel 10-bit SAR ADC. Each of interrupt sources has a unique interrupt vector.  Serial Interface: SIO, UART, MSP  Build in Embedded ICE function.  I/O pin configuration Bi-directional: P0, P1, P4, P5.  Four system clocks Wakeup: P0, P1 level change. External high clock: RC type up to 10MHz Pull-up resisters: P0, P1, P4, P5. External high clock: Crystal type up to 16MHz External interrupt: P0.0, P0.1 Internal high clock: RC type 16MHz ADC input pin: AIN0~AIN11. Internal low clock: RC type 16KHz  Four operating modes  Fcpu (Instruction cycle) Normal mode: Both high and low clock active Fcpu = Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16, Slow mode: Low clock only Fhosc/32, Fhosc/64, Fhosc/128 Sleep mode: Both high and low clock stop  On chip watchdog timer and clock source Green mode: Periodical wakeup by timer  1.8V/2.4V/3.3V 3-level LVD with trim.  Package (Chip form support) PDIP 32 pin  Powerful instructions LQFP 32 pin Instruction’s length is one word. QFN 32 pin Most of instructions are one cycle only. SKDIP 28 pin All ROM area JMP instruction. SOP 28 pin All ROM area lookup table function (MOVC). SSOP 28 pin QFN 28 pin DIP 20 pin SOP 20 pin
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