module light(R2,R1,R0,L2,L1,L0,CLK,I3,I2,I1);
input CLK;
input I3,I2,I1;
output R2,R1,R0,L2,L1,L0;
reg R2,R1,R0,L2,L1,L0;
wire [1:0] A;
assign A[1]=(~I3&I2)|(I3);
assign A[0]=(~I3&~I2&I1)|(I3);
reg [2:0] Q;
reg [2:0] STATE,NEXT_STATE;
parameter
STATE0=3'b000,
STATE1=3'b001,
STATE2=3'b010,
STATE3=3'b011,
STATE4=3'b100,
STATE5=3'b101,
STATE6=3'b110,
STATE7=3'b111;
always @ (STATE)
begin
case (STATE)
STATE0:
begin NEXT_STATE<=STATE1;end
STATE1:
begin NEXT_STATE<=STATE2;end
STATE2:
begin NEXT_STATE<=STATE4;end
STATE3:
begin NEXT_STATE<=STATE6;end
STATE4:
begin NEXT_STATE<=STATE1;end
STATE5:
begin NEXT_
汽车尾灯控制电路设计的第一种方法
最新推荐文章于 2025-01-11 23:34:09 发布