General layout Guidelines

General layout Guidelines

1. Diode/LED footprint needs to have polarity. The symbol of the diode can be present inside the outline.

2. Positive polarity for tantalum and electrolytic capacitors need to be present in the footprint. Any through hole/Size A and upper size capacitors need to have polarity.

3. Headers/Connectors need to have pin 1 marking in big font. If the connector has alphanumeric pin numbering then A1, B1, etc., need to be present. Place “1” text near the pin 1 even if the header has square pad as pin 1 indication.

4. ICs need to have pin 1 marking. In case of the alphanumeric pin numbering place A1 text outside the outline of the component. A circle as a pin 1 number indication is also acceptable.

5. When assigning the pin numbering to the footprint of a transistor always refers to the datasheet of the component and schematic. Most of the times the pin numbering of the schematic will not match with the datasheet.

6. Test points are used for probing the signals during the debug process. Always place test points on the TOP.

7. LED’s are status indicators. Always LED’s should be placed on the TOP.

8. Minimum of three fiducial marks needs to be present on TOP and BOTTOM layers. Fiducials marks are used for the x-y calibration during the component placement on the SMT machine. It is a good practice to provide local fiducials for the BGAs with higher pin count.

9. Never put silkscreen/reference inside the socket outline of a BGA.

10. Thermal pads need to be connector to either ground/power as per the datasheet. Most of the times schematic will not include an extra pin for the thermal pad. In such situation the connectivity of the thermal pad will be lost next time you import the netlist. Inform customer to include an extra pin for the thermal pad in the schematic.

11. When creating footprints always name the decals same as the device name provided in the netlist. If the netlist has spaces in the device name, then replace it with underscore.

12. When placing decoupling capacitors refer to the schematic. It will give you an indication of which capacitors need to couple with which devices. Always place the smaller value capacitors near the device and progressively larger values away from the device. Most of the times decoupling capacitors are placed near the power pins of the device than the ground pins. When connecting the decoupling capacitor to the device pin provide thicker trace as possible. It will help in reducing the inductance of the trace. If the decoupling capacitor is placed far away from the device then connect the capacitor directly to the plane.

13. Always use a big via for the power traces when compared to the signal vias. On the input and output of the regulators use multiple vias to connect to the plane.

14. For the Size A and bigger capacitors use more than one via to the plane.

15. Series terminations should always be placed near the driver. Parallel termination should be placed near the load. Most of the devices including FPGAs have in-built terminations on the die. Termination components (resistor in most of the cases) should be placed as close to the device as possible.

16. Sense lines should never connect to the plane directly near the connector or the regulator. It should always be run as a trace and should be connected near the load.

17. Never route traces over a split plane. It increases the return path of the signal, which results in higher inductance of the trace.

18. Whenever possible try to maintain as much spacing between the traces as possible. The general rule of thumb is to maintain 2H spacing between the adjacent traces where H is the distance of the trace from the closest plane.

19. Never route traces on the edge of the board. As a rule of thumb maintain 3H spacing from the edge of the plane to the trace. Again H is the vertical distance between the trace and the plane.

20. Try to avoid stubs as much as possible. Stubs cause reflections in the transmission lines. Keep stubs shorter than 1/8 of the rise distance. Always perform daisy chain routing wherever possible.

21. Whenever possible route in the inner layers. Avoid routing on the TOP and BOTTOM layers.

22. Add at least 4 mounting holes on the corners of the board.

23. Switches/Push buttons needs to be present on the TOP unless otherwise specified.

24. Make sure the differential traces are routed above ground layers.

25. Stubs should be avoided. Max stub length should be specified for all critical traces.

26. Test points, that are added after the signals are routed, often end up being stubs.