DDR2 ROUTING GUIDELINES

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转载最新推荐文章于 2026-07-25 15:51:25 发布 821 阅读 AI 写同款· GEO 优化 ›

TMS320C6455之DDR2内存控制器基于TMS320C6455DDR2内存控制器的介绍前言： DDR2内存控制器是连接DDR2内存设备的接口，内存的类型有DDR1 SDRAM，DDR2 SDRAM，并且内存设备要符合JESD79-2B 标准。SDR SDRAM、SBSRAM和异步存储器，不支持。DDR2内存控制器的内存可用于存储程序和数据。阅读详情

DDR2 ROUTING GUIDELINES:

All signals from the FPGA to DDR2 modules and to the VTT termination resistors are 50-ohm transmission lines referenced to the ground planes.
The ground planes must be continuous between the FPGA, DDR, and VTT termination resistors with no line breaks in the planes.
Total line length (incl. any series resistors) from the FPGA balls to the DDR2 nearest the FPGA is 2.5”min. If this just not possible then 1.9” absolute min can be used. Best would be for all line lengths from FPGA to DDR nearest the FPGA to be the same length. (incl. any series resistors) to within 50mils.
Signal pairs with the signal names: DDR1_CLK0_x, DDR1_CLK1_x, DDR1_CLK2_x must be routed as a differential pairs. (incl. the series resistors and traces continuing on to the DDR2 modules) and be pair matched length to within 50mils.
Series Resistors should be close to the device (FPGA) and the parallel resistors should close to the load termination.
The Address lines (ADR0: ADR12) from FPGA go to series resistor. From the series resistor it goes to DDR2 module and from DDR module it goes to parallel termination resistor.
Trace space to other non-DDR2 data groups = 25 mil.
Trace space requirements within the DDR2 data group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on trace width of 5 mil.
Trace space requirements within the DDR2 address/cmd group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on trace width of 5 mil.
Match all segment lengths between differential pairs along the entire length of the pair.
Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.
Differential Impedance = 100–120 (50–60 Ωsingle ended with proper spacing).
Do not divide the two halves of the diff pair between layers.
Global items—do not route any DDR2 signals over splits or voids.
Minimum of 20–25 mils recommended for VREF.
Routing order within the DDR2 interface:
1)Data, 2) Address/Command, 3) Control, 4) Clocks, and 5) Power
Construct the signal routing topologies for the groups like those found on unbuffered DIMM modules.
When placing components, optimize placement of the discrete to favor the data bus (analogous to DIMM topologies).
Optional: Pin-swap within a given byte lane to optimize the data bus routes further.