(z)如何在SignalTAP II中保留特定节点

最新推荐文章于 2020-04-10 19:24:50 发布

原创最新推荐文章于 2020-04-10 19:24:50 发布 · 213 阅读

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本文详细介绍了在使用SignalTAPII进行调试时遇到的问题，即调试用的逻辑（如计数器）被Quartus II软件优化而不在调试波形中出现。文中提供了通过在源HDL代码中添加'keep'或'preserve'属性来强制保留这些信号的方法，以确保调试过程的顺利进行。

Original address: http://blog.ednchina.com/riple/74826/message.aspx

在使用SignalTAP II的过程中，我经常发现一些用于调试的逻辑（比如调试用的计数器）会被优化掉，不能出现在调试波形中。在Altera的一篇文档中，发现了以下关键信息:

In the logic synthesis stage, the Quartus II software may optimize away signals that you are trying to analyze with the SignalTap II Embedded Logic Analyzer. If this occurs, you will see a compilation error. You can force the Quartus II software to preserve these signals by adding the keep or preserve attribute in the source HDL to the signals you want to monitor.

The keep attribute is used for a wire or net node. For example:
In Verilog:
    wire my_wire /* synthesis keep = 1 */:
In VHDL:
    signal my_signal: bit;
    attribute syn_keep : boolean;
    attribute syn_keep of my_signal: signal is true;

The preserve attribute is used for a register. For example:
In Verilog:
    reg my_reg /* synthesis preserve = 1 */:
In VHDL:
    signal my_reg: stdlogic;
    attribute preserve : boolean;
    attribute preserve of my_signal: signal is true;

谢谢, riple!!