arm 清除cache情况

reason：：

      Changing the memory configuration of a system may require cleaning or flushing a
cache. The need to clean or flush a cache results directly from actions like changing the
access permission, cache, and buffer policy, or remapping virtual addresses.
The cache may also need cleaning or flushing before the execution of self-modifying
code in a split cache. Self-modifying code includes a simple copy of code from one location
to another. The need to clean or flush arises from two possible conditions: First, the self-
modifying code may be held in the D-cache and therefore be unavailable to load from
mainmemory as an instruction. Second, existing instructions in the I-cachemaymask new
instructions written to main memory.
If a cache is using awriteback policy and self-modifying code iswritten tomainmemory,
the first step is to write the instructions as a block of data to a location in main memory. At
a later time, the program will branch to this memory and begin executing from that area of
memory as an instruction stream. During the first write of code to main memory as data, it
may be written to cache memory instead; this occurs in an ARM cache if valid cache lines
exist in cache memory representing the location where the self-modifying code is written.
The cache lines are copied to the D-cache and not to main memory. If this is the case, then
when the programbranches to the location where the self-modifying code should be, it will
execute old instructions still present because the self-modifying code is still in the D-cache.
To prevent this, clean the cache, which forces the instructions stored as data into main
memory, where they can be read as an instruction stream.
If theD-cache has been cleaned, newinstructions are present inmainmemory.However,
the I-cache may have valid cache lines stored for the addresses where the new data (code)
waswritten. Consequently, a fetch of the instruction at the address of the copied codewould
retrieve the old code from the I-cache and not the new code from main memory. Flush the
I-cache to prevent this from happening.

由于icache dcache main memory  3个是相互独立的，必须要保持它们的一致性，所以有了相应的clean flush操作。

cache line里面有

 There are two common status
bits within the cache: the valid bit and the dirty bit. The valid bit is set when the associated
cache line contains activememory. The dirty bit is active when the cache is using a writeback
policy and new data has been written to cache memory.

There are two policies a cache controller uses to allocate a cache line on a cache
miss. A read-allocate policy allocates a cache line when data is read from main memory.
A write-allocate policy allocates a cache line on a write to main memory.
ARM uses the term clean to mean forcing a copyback of data in the D-cache to main
memory. ARM uses the term flush to mean invalidating the contents of a cache.