代码模板-Linux内核中代码流程如何sleep随机时间?(#include <linux/delay.h> usleep_range(1000, 2000))

背景

linux内核提供了很多delay的技术,本文是第二篇使用usleep_range的方式,之前还提供过一种用completion的timeout机制实现的。usleep_range提供了一个休眠的时间范围,而不是固定的延迟时间

基础机制

usleep_range 是 Linux 内核中用于微秒级休眠的宏,它接受两个参数,分别是最小和最大微秒数。这个宏在内核的不同版本中可能有所不同,但基本思想是提供一个随机的休眠时间,以避免时钟同步问题。

头文件:

#include <linux/delay.h>

使用方式:

usleep_range(1000, 2000);  //表示1000 和 2000 微秒之间

模块代码

C语言代码:simple_sleep_module.c

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/uaccess.h>
#include <linux/delay.h>

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Your Name");
MODULE_DESCRIPTION("A simple Linux module using usleep_range");
MODULE_VERSION("0.01");

static void simple_sleep_function(void) {
    printk(KERN_INFO "simple_sleep_function: Sleeping for a random time between 1000 and 2000 microseconds\n");
    usleep_range(1000, 2000); // Sleep for a random time between 1000 and 2000 microseconds
    printk(KERN_INFO "simple_sleep_function: Woke up\n");
}

static int __init simple_sleep_init(void) {
    simple_sleep_function();
    return 0;
}

static void __exit simple_sleep_exit(void) {
    printk(KERN_INFO "simple_sleep_module: Exiting\n");
}

module_init(simple_sleep_init);
module_exit(simple_sleep_exit);

Makefile

obj-m += simple_sleep_module.o

all:
	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules

clean:
	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

实战

  • 编译
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  • 加载
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  • 卸载
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综述

linux内核提供了很多delay的技术,本文是第二篇使用usleep_range的方式,之前还提供过一种用completion的timeout机制实现的。
更多内核中sleep玩法参考兄弟篇:https://blog.youkuaiyun.com/essencelite/article/details/140054928

#define pr_fmt(fmt) "gpio-privacy: " fmt #include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/mutex.h> #include <linux/of_irq.h> #include <linux/of_gpio.h> #include <linux/of_platform.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/input.h> #define DEFAULT_DEBOUNCE_INTERVAL 5 enum privacy_state { PRIVACY_STATE_OFF = 0, /* HW privacy is OFF */ PRIVACY_STATE_ON, /* HW privacy is ON */ }; struct privacy_state_warning_event { const char *desc; unsigned int input_type; unsigned int code; unsigned int input_value; struct input_dev *input_dev; struct work_struct work; struct privacy_priv *priv; }; struct privacy_state_event { const char *desc; unsigned int input_type; unsigned int code; struct input_dev *input_dev; struct work_struct work; int state_gpio; enum of_gpio_flags state_gpio_flags; struct privacy_priv *priv; }; struct privacy_button_event { const char *desc; unsigned int code; unsigned int input_type; int debounce_interval; struct input_dev *input_dev; struct delayed_work work; bool wakeup_capable; int button_gpio; enum of_gpio_flags button_gpio_flags; int last_button_event; unsigned long last_button_press_time; unsigned long last_button_release_time; struct privacy_priv *priv; }; struct privacy_priv { int enable_gpio; enum of_gpio_flags enable_gpio_flags; int enable_gpio_toggle_duration; int privacy_event_max_press_duration; int auto_toggle_enable_gpio_time; bool is_desired_privacy_state_on; struct mutex mutex; struct privacy_state_warning_event *state_warning_event; struct privacy_state_event *state_event; struct privacy_button_event *button_event; struct delayed_work work; }; /* Forward declarations: */ static enum privacy_state __privacy_state(struct privacy_priv *priv); static int __set_privacy_enable(struct privacy_priv *priv); static void handle_privacy_button_event(struct privacy_button_event *button_event, bool button_pressed, bool do_toggle) { enum privacy_state cur_state; struct privacy_priv *priv = button_event->priv; struct privacy_state_warning_event *state_warning_event = priv->state_warning_event; unsigned long button_press_duration; unsigned long last_button_press_time; bool is_desired_privacy_state_on; cur_state = __privacy_state(priv); if (button_pressed) { mutex_lock(&priv->mutex); button_event->last_button_press_time = jiffies; /* With the Silego chip, we only know whether we are entering * privacy state on the button press because on button press * Silego locks the current state, so save this off because * we will need this info on button release. */ if (cur_state == PRIVACY_STATE_OFF) priv->is_desired_privacy_state_on = true; mutex_unlock(&priv->mutex); pr_debug("%s: privacy button PRESSED cur_state=%d\n", __func__, cur_state); return; } pr_debug("%s: privacy button RELEASED cur_state=%d\n", __func__, cur_state); /* privacy button released ! */ mutex_lock(&priv->mutex); button_event->last_button_release_time = jiffies; last_button_press_time = button_event->last_button_press_time; is_desired_privacy_state_on = priv->is_desired_privacy_state_on; priv->is_desired_privacy_state_on = false; mutex_unlock(&priv->mutex); if (priv->privacy_event_max_press_duration > 0) { button_press_duration = last_button_press_time + msecs_to_jiffies(priv->privacy_event_max_press_duration); /* Ignore long press because it might be for Power Event or Factory Reset */ if (time_after(jiffies, button_press_duration)) { pr_debug("%s: POWER EVENT: cur_state=%d\n", __func__, cur_state); is_desired_privacy_state_on = false; } } if (is_desired_privacy_state_on && do_toggle) { if (state_warning_event != NULL) { pr_debug("%s: state_warning schedule work: cur_state=%d\n", __func__, cur_state); schedule_work(&state_warning_event->work); } if (priv->auto_toggle_enable_gpio_time >= 0) { pr_info("%s: auto-toggle-enable schedule work\n", __func__); schedule_delayed_work(&priv->work, msecs_to_jiffies(priv->auto_toggle_enable_gpio_time)); } } } static void privacy_work_func(struct work_struct *work) { struct privacy_priv *priv = container_of(work, struct privacy_priv, work.work); mutex_lock(&priv->mutex); pr_info("%s: privacy state enable immediately\n", __func__); __set_privacy_enable(priv); mutex_unlock(&priv->mutex); } static void privacy_state_warning_event_work_func(struct work_struct *work) { struct privacy_state_warning_event *state_warning_event = container_of(work, struct privacy_state_warning_event, work); pr_info("%s: sending state warning to userspace. input_type=0x%x code=0x%x\n", __func__, state_warning_event->input_type, state_warning_event->code); if (state_warning_event->input_type == EV_KEY || state_warning_event->input_type == EV_SW) { /* * EV_KEY key events and EV_SW switch events require a full transition from 0 to 1 * and then 1 to 0 in order to get future events */ input_event(state_warning_event->input_dev, state_warning_event->input_type, state_warning_event->code, 1); input_sync(state_warning_event->input_dev); input_event(state_warning_event->input_dev, state_warning_event->input_type, state_warning_event->code, 0); input_sync(state_warning_event->input_dev); } else if (state_warning_event->input_type == EV_MSC || state_warning_event->code == MSC_RAW) { /* * EV_MSC events only send a single event with 'input value' from dts */ input_event(state_warning_event->input_dev, state_warning_event->input_type, state_warning_event->code, state_warning_event->input_value); input_sync(state_warning_event->input_dev); } } static void privacy_state_event_work_func(struct work_struct *work) { bool value; struct privacy_state_event *state_event = container_of(work, struct privacy_state_event, work); value = gpio_get_value_cansleep(state_event->state_gpio); if (state_event->state_gpio_flags & OF_GPIO_ACTIVE_LOW) value = !value; input_event(state_event->input_dev, state_event->input_type, state_event->code, value); input_sync(state_event->input_dev); } static void privacy_button_event_work_func(struct work_struct *work) { int value; struct privacy_button_event *button_event = container_of(work, struct privacy_button_event, work.work); value = gpio_get_value_cansleep(button_event->button_gpio); if (unlikely(value < 0)) { /* * gpio read can fail, however we should report button * press in order to notify userspace that privacy * state has been changed. force it to * !button_event->last_button_event for that case in the hope * we just missed one press or release. */ pr_warn_ratelimited("gpio-privacy: gpio %d read failed=%d\n", button_event->button_gpio, value); value = !button_event->last_button_event; } else if (button_event->button_gpio_flags & OF_GPIO_ACTIVE_LOW) { value = !value; } if (button_event->last_button_event == value) { /* * We can reach here when : * 1) previous press/release has been canceled due to * debouce interval. * 2) gpio_get_value() failed. * 3) button is pressed and released then we got irqs together. * * We should report button press by all means in order for * userspace to be notified about new privacy mode change. * Thus send out an artificial event. * * Unlike the mute enable case, mute disable takes no delay * to complete the mode switching. Thus if the mute button is * already released, read of the current mute status gives us * the newly switched status. In this case, we shouldn't read * the current privacy status and toggle. */ handle_privacy_button_event(button_event, !value, false); input_event(button_event->input_dev, button_event->input_type, button_event->code, !value); input_sync(button_event->input_dev); } else { button_event->last_button_event = value; } handle_privacy_button_event(button_event, value, true); input_event(button_event->input_dev, button_event->input_type, button_event->code, value); input_sync(button_event->input_dev); if (button_event->wakeup_capable) pm_relax(button_event->input_dev->dev.parent); } static irqreturn_t privacy_state_interrupt(int irq, void *arg) { struct privacy_state_event *state_event = arg; schedule_work(&state_event->work); return IRQ_HANDLED; } static irqreturn_t privacy_button_interrupt(int irq, void *arg) { struct privacy_button_event *button_event = arg; if (button_event->wakeup_capable) pm_stay_awake(button_event->input_dev->dev.parent); cancel_delayed_work(&button_event->work); schedule_delayed_work(&button_event->work, msecs_to_jiffies(button_event->debounce_interval)); return IRQ_HANDLED; } static int privacy_request_interrupts(struct platform_device *pdev) { int ret; struct privacy_priv *priv = platform_get_drvdata(pdev); struct privacy_state_event *state_event = priv->state_event; struct privacy_button_event *button_event = priv->button_event; ret = devm_request_any_context_irq(&pdev->dev, gpio_to_irq(state_event->state_gpio), privacy_state_interrupt, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "gpio-privacy-state", state_event); if (ret < 0) return ret; ret = devm_request_any_context_irq(&pdev->dev, gpio_to_irq(button_event->button_gpio), privacy_button_interrupt, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "gpio-privacy", button_event); if (ret < 0) return ret; return 0; } static int privacy_setup_state_warning_event(struct platform_device *pdev) { int ret; struct input_dev *input; struct device *dev = &pdev->dev; struct privacy_priv *priv = platform_get_drvdata(pdev); /* state_warning_event is optional dts node */ if (priv->state_warning_event == NULL) return 0; INIT_WORK(&priv->state_warning_event->work, privacy_state_warning_event_work_func); input = devm_input_allocate_device(dev); if (!input) return -ENOMEM; input->name = "gpio-privacy-state-warning"; input->dev.parent = &pdev->dev; input_set_capability(input, priv->state_warning_event->input_type, priv->state_warning_event->code); priv->state_warning_event->input_dev = input; priv->state_warning_event->priv = priv; ret = input_register_device(input); if (ret) return ret; return 0; } static int privacy_setup_state_event(struct platform_device *pdev) { int ret; struct input_dev *input; struct device *dev = &pdev->dev; struct privacy_priv *priv = platform_get_drvdata(pdev); INIT_WORK(&priv->state_event->work, privacy_state_event_work_func); input = devm_input_allocate_device(dev); if (!input) return -ENOMEM; input->name = "gpio-privacy-state"; input->dev.parent = &pdev->dev; input_set_capability(input, priv->state_event->input_type, priv->state_event->code); priv->state_event->input_dev = input; priv->state_event->priv = priv; ret = input_register_device(input); if (ret) return ret; /* seed initial value if already in a muted state */ if (priv->state_event->input_type == EV_SW && __privacy_state(priv)) { input_event(priv->state_event->input_dev, priv->state_event->input_type, priv->state_event->code, 1); input_sync(priv->state_event->input_dev); } return 0; } static int privacy_setup_button_event(struct platform_device *pdev) { int ret; struct input_dev *input; struct device *dev = &pdev->dev; struct privacy_priv *priv = platform_get_drvdata(pdev); INIT_DELAYED_WORK(&priv->button_event->work, privacy_button_event_work_func); input = devm_input_allocate_device(dev); if (!input) return -ENOMEM; input->name = "gpio-privacy-button"; input->dev.parent = &pdev->dev; input_set_capability(input, priv->button_event->input_type, priv->button_event->code); priv->button_event->input_dev = input; priv->button_event->priv = priv; ret = input_register_device(input); if (ret) return ret; return 0; } #ifdef CONFIG_OF static int privacy_state_warning_event_parse_of(struct platform_device *pdev) { struct device_node *node; struct device_node *state_warning_event_node; struct privacy_priv *priv = platform_get_drvdata(pdev); node = pdev->dev.of_node; state_warning_event_node = of_get_child_by_name(node, "state_warning_event"); if (!state_warning_event_node) { /* state warning event is optional in dts */ dev_warn(&pdev->dev, "No state warning event configured in dts\n"); return 0; } priv->state_warning_event = devm_kzalloc(&pdev->dev, sizeof(*priv->state_warning_event), GFP_KERNEL); if (!priv->state_warning_event) return -ENOMEM; priv->state_warning_event->desc = of_get_property(state_warning_event_node, "label", NULL); if (of_property_read_u32(state_warning_event_node, "linux,input-type", &priv->state_warning_event->input_type)) priv->state_warning_event->input_type = EV_KEY; if (of_property_read_u32(state_warning_event_node, "linux,code", &priv->state_warning_event->code)) return -EINVAL; if (priv->state_warning_event->input_type == EV_MSC && priv->state_warning_event->code == MSC_RAW) { if (of_property_read_u32(state_warning_event_node, "linux,input-value", &priv->state_warning_event->input_value)) return -EINVAL; } return 0; } static int privacy_state_event_parse_of(struct platform_device *pdev) { int ret; enum of_gpio_flags flags; struct device_node *node; struct device_node *state_event_node; struct privacy_priv *priv = platform_get_drvdata(pdev); node = pdev->dev.of_node; state_event_node = of_get_child_by_name(node, "state_event"); if (!state_event_node) { dev_err(&pdev->dev, "No state event configured in dts\n"); return -EINVAL; } priv->state_event = devm_kzalloc(&pdev->dev, sizeof(*priv->state_event), GFP_KERNEL); if (!priv->state_event) return -ENOMEM; priv->state_event->desc = of_get_property(state_event_node, "label", NULL); if (of_property_read_u32(state_event_node, "linux,input-type", &priv->state_event->input_type)) priv->state_event->input_type = EV_KEY; if (of_property_read_u32(state_event_node, "linux,code", &priv->state_event->code)) return -EINVAL; priv->state_event->state_gpio = of_get_gpio_flags(state_event_node, 0, &flags); if (!gpio_is_valid(priv->state_event->state_gpio)) { dev_err(&pdev->dev, "No state gpios configured in dts\n"); return -EINVAL; } priv->state_event->state_gpio_flags = flags; ret = devm_gpio_request_one(&pdev->dev, priv->state_event->state_gpio, GPIOF_IN, "privacy-state-gpio"); if (ret) return ret; dev_info(&pdev->dev, "state gpio %d configured.\n", priv->state_event->state_gpio); return 0; } static int privacy_button_event_parse_of(struct platform_device *pdev) { int ret; enum of_gpio_flags flags; struct device_node *node; struct device_node *button_event_node; struct privacy_priv *priv = platform_get_drvdata(pdev); node = pdev->dev.of_node; button_event_node = of_get_child_by_name(node, "button_event"); if (!button_event_node) { dev_err(&pdev->dev, "No button event configured in dts\n"); return -EINVAL; } priv->button_event = devm_kzalloc(&pdev->dev, sizeof(*priv->button_event), GFP_KERNEL); if (!priv->button_event) return -ENOMEM; priv->button_event->desc = of_get_property(button_event_node, "label", NULL); if (of_property_read_u32(button_event_node, "linux,input-type", &priv->button_event->input_type)) priv->button_event->input_type = EV_KEY; if (of_property_read_u32(button_event_node, "linux,code", &priv->button_event->code)) return -EINVAL; if (of_property_read_u32(button_event_node, "debounce-interval", &priv->button_event->debounce_interval)) priv->button_event->debounce_interval = DEFAULT_DEBOUNCE_INTERVAL; priv->button_event->button_gpio = of_get_gpio_flags(button_event_node, 0, &flags); if (!gpio_is_valid(priv->button_event->button_gpio)) { dev_err(&pdev->dev, "No button gpios configured in dts\n"); return -EINVAL; } priv->button_event->button_gpio_flags = flags; ret = devm_gpio_request_one(&pdev->dev, priv->button_event->button_gpio, GPIOF_IN, "privacy-button-gpio"); if (ret) return ret; dev_info(&pdev->dev, "button gpio %d configured.\n", priv->button_event->button_gpio); priv->button_event->wakeup_capable = of_property_read_bool(button_event_node, "wakeup-source"); return 0; } static int privacy_parse_of(struct platform_device *pdev) { enum of_gpio_flags flags; int gpio, ret, gpio_init_val; struct privacy_priv *priv = platform_get_drvdata(pdev); gpio = of_get_named_gpio_flags(pdev->dev.of_node, "enable-gpio", 0, &flags); if (!gpio_is_valid(gpio)) { dev_err(&pdev->dev, "No enable gpio configured in dts\n"); return -EPROBE_DEFER; } if (flags & OF_GPIO_ACTIVE_LOW) gpio_init_val = GPIOF_OUT_INIT_HIGH; else gpio_init_val = GPIOF_OUT_INIT_LOW; ret = devm_gpio_request_one(&pdev->dev, gpio, gpio_init_val, "privacy-enable-gpio"); if (ret) return ret; priv->enable_gpio = gpio; priv->enable_gpio_flags = flags; priv->is_desired_privacy_state_on = false; if (of_property_read_u32(pdev->dev.of_node, "enable-gpio-toggle-duration", &priv->enable_gpio_toggle_duration)) priv->enable_gpio_toggle_duration = 0; if (of_property_read_u32(pdev->dev.of_node, "auto-toggle-enable-gpio-time", &priv->auto_toggle_enable_gpio_time)) priv->auto_toggle_enable_gpio_time = -1; if (of_property_read_u32(pdev->dev.of_node, "privacy-event-max-press-duration", &priv->privacy_event_max_press_duration)) priv->privacy_event_max_press_duration = 0; if (priv->auto_toggle_enable_gpio_time >= 0) INIT_DELAYED_WORK(&priv->work, privacy_work_func); return 0; } #else static int privacy_button_event_parse_of(struct platform_device *pdev) { return -EINVAL; } static int privacy_parse_of(struct platform_device *pdev) { return -EINVAL; } #endif static enum privacy_state __privacy_state(struct privacy_priv *priv) { struct privacy_state_event *state_event = priv->state_event; int value = gpio_get_value_cansleep(state_event->state_gpio); if ((!value && state_event->state_gpio_flags & OF_GPIO_ACTIVE_LOW) || (value && !(state_event->state_gpio_flags & OF_GPIO_ACTIVE_LOW))) /* return true when privacy state is on */ return PRIVACY_STATE_ON; return PRIVACY_STATE_OFF; } static int __set_privacy_enable(struct privacy_priv *priv) { int i = 0; int value = 1; /* default to 1, active high, unless proven otherwise */ const int max_wait = 100; pr_info("%s: Enter\n", __func__); if (priv->enable_gpio_flags & OF_GPIO_ACTIVE_LOW) value = 0; gpio_set_value_cansleep(priv->enable_gpio, value); if (priv->enable_gpio_toggle_duration > 0) { /* * toggle enable_gpio for specified duration but do not * wait for privacy enabled */ if (priv->enable_gpio_toggle_duration < 20) usleep_range((priv->enable_gpio_toggle_duration * 1000), (priv->enable_gpio_toggle_duration * 1000) + 100); else msleep(priv->enable_gpio_toggle_duration); } else { /* * wait for privacy enabled for up to 100ms or when * privacy state is set (which ever comes first) */ while (i < max_wait) { if (__privacy_state(priv)) break; usleep_range(1000, 1100); i++; } } gpio_set_value_cansleep(priv->enable_gpio, !value); pr_info("%s: Leave\n", __func__); if (i == max_wait) return -ETIMEDOUT; return 0; } static enum privacy_state privacy_state(struct device *dev) { enum privacy_state cur_state; struct platform_device *pdev = to_platform_device(dev); struct privacy_priv *priv = platform_get_drvdata(pdev); mutex_lock(&priv->mutex); cur_state = __privacy_state(priv); mutex_unlock(&priv->mutex); return cur_state; } static ssize_t show_privacy_state(struct device *dev, struct device_attribute *attr, char *buf) { enum privacy_state state = privacy_state(dev); return snprintf(buf, PAGE_SIZE, "%d\n", state); } static int set_privacy_enable(struct device *dev) { int ret = 0; struct platform_device *pdev = to_platform_device(dev); struct privacy_priv *priv = platform_get_drvdata(pdev); mutex_lock(&priv->mutex); pr_info("%s: privacy state enable immediately\n", __func__); __set_privacy_enable(priv); mutex_unlock(&priv->mutex); return ret; } static ssize_t store_privacy_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { int enable, ret; if (!kstrtoint(buf, 10, &enable)) { /* * Don't allow userspace to turn off Privacy Mode because * privacy hardware circuit won't allow it. */ if (enable == PRIVACY_STATE_OFF) return -EINVAL; ret = set_privacy_enable(dev); if (ret) return ret; } else { return -EINVAL; } return count; } static DEVICE_ATTR(enable, S_IWUSR | S_IWGRP, NULL, store_privacy_enable); static DEVICE_ATTR(state, S_IRUGO, show_privacy_state, NULL); static struct attribute *gpio_privacy_attrs[] = { &dev_attr_enable.attr, &dev_attr_state.attr, NULL, }; static struct attribute_group gpio_privacy_attr_group = { .attrs = gpio_privacy_attrs, }; static int gpio_privacy_probe(struct platform_device *pdev) { int ret; struct privacy_priv *priv; struct device *dev = &pdev->dev; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; mutex_init(&priv->mutex); platform_set_drvdata(pdev, priv); ret = privacy_parse_of(pdev); if (ret) { pr_err("failed to parse device tree = %d\n", ret); return ret; } ret = privacy_state_warning_event_parse_of(pdev); if (ret) { pr_err("failed to parse state warning event device tree = %d\n", ret); return ret; } ret = privacy_state_event_parse_of(pdev); if (ret) { pr_err("failed to parse state event device tree = %d\n", ret); return ret; } ret = privacy_button_event_parse_of(pdev); if (ret) { pr_err("failed to parse button event device tree = %d\n", ret); return ret; } ret = privacy_setup_state_warning_event(pdev); if (ret) { pr_err("failed to setup state warning event = %d\n", ret); return ret; } ret = privacy_setup_state_event(pdev); if (ret) { pr_err("failed to setup state event = %d\n", ret); return ret; } ret = privacy_setup_button_event(pdev); if (ret) { pr_err("failed to setup button event = %d\n", ret); return ret; } ret = privacy_request_interrupts(pdev); if (ret) { pr_err("failed to request interrupt = %d\n", ret); return ret; } ret = sysfs_create_group(&dev->kobj, &gpio_privacy_attr_group); if (ret) { pr_err("failed to create sysfs group = %d\n", ret); return ret; } device_init_wakeup(&pdev->dev, priv->button_event->wakeup_capable); return 0; } static int gpio_privacy_remove(struct platform_device *pdev) { struct privacy_priv *priv; struct device *dev = &pdev->dev; struct privacy_state_warning_event *state_warning_event; struct privacy_state_event *state_event; struct privacy_button_event *button_event; priv = platform_get_drvdata(pdev); state_warning_event = priv->state_warning_event; state_event = priv->state_event; button_event = priv->button_event; if (priv->auto_toggle_enable_gpio_time >= 0) cancel_delayed_work_sync(&priv->work); if (state_warning_event != NULL) cancel_work_sync(&state_warning_event->work); cancel_work_sync(&state_event->work); cancel_delayed_work_sync(&button_event->work); sysfs_remove_group(&dev->kobj, &gpio_privacy_attr_group); if (state_warning_event != NULL) pm_relax(state_warning_event->input_dev->dev.parent); pm_relax(state_event->input_dev->dev.parent); pm_relax(button_event->input_dev->dev.parent); mutex_destroy(&priv->mutex); return 0; } #ifdef CONFIG_PM_SLEEP static int gpio_privacy_suspend(struct device *dev) { struct privacy_priv *priv; struct privacy_state_event *state_event; struct privacy_button_event *button_event; struct platform_device *pdev = to_platform_device(dev); priv = platform_get_drvdata(pdev); state_event = priv->state_event; button_event = priv->button_event; if (button_event->wakeup_capable) { int error; enable_irq_wake(gpio_to_irq(button_event->button_gpio)); error = irq_set_irq_type(gpio_to_irq(button_event->button_gpio), IRQ_TYPE_EDGE_BOTH); if (error) { pr_err("%s: failed to set wakeup trigger for gpio-privacy, err=%d\n", __func__, error); disable_irq_wake(gpio_to_irq(button_event->button_gpio)); return error; } } return 0; } static int gpio_privacy_resume(struct device *dev) { struct privacy_priv *priv; struct privacy_state_event *state_event; struct privacy_button_event *button_event; struct platform_device *pdev = to_platform_device(dev); priv = platform_get_drvdata(pdev); state_event = priv->state_event; button_event = priv->button_event; if (button_event->wakeup_capable) { int error; error = irq_set_irq_type(gpio_to_irq(button_event->button_gpio), IRQ_TYPE_EDGE_BOTH); if (error) pr_err("%s: failed to restore interrupt trigger gpio-privacy, err=%d\n", __func__, error); disable_irq_wake(gpio_to_irq(button_event->button_gpio)); } return 0; } #endif #ifdef CONFIG_OF static const struct of_device_id privacy_of_table[] = { { .compatible = "gpio-privacy", }, { }, }; MODULE_DEVICE_TABLE(of, privacy_of_table); #endif #ifdef CONFIG_PM_SLEEP static SIMPLE_DEV_PM_OPS(gpio_privacy_pm_ops, gpio_privacy_suspend, gpio_privacy_resume); #endif static struct platform_driver gpio_privacy_driver = { .driver = { .name = "gpio-privacy", #ifdef CONFIG_PM_SLEEP .pm = &gpio_privacy_pm_ops, #endif .of_match_table = of_match_ptr(privacy_of_table), }, .probe = gpio_privacy_probe, .remove = gpio_privacy_remove, }; static int __init gpio_privacy_init(void) { return platform_driver_register(&gpio_privacy_driver); } static void __exit gpio_privacy_exit(void) { platform_driver_unregister(&gpio_privacy_driver); } module_init(gpio_privacy_init); module_exit(gpio_privacy_exit); MODULE_LICENSE("GPL"); how to enable pr_debug ?
08-16
/* * Copyright (c) 2018 Actions Semiconductor Co., Ltd * * SPDX-License-Identifier: Apache-2.0 */ /** * @brief PWM controller driver for Actions SoC */ #include <errno.h> #include <sys/__assert.h> #include <stdbool.h> #include <kernel.h> #include <device.h> #include <init.h> #include <drivers/pwm.h> #include <soc.h> #include <drivers/dma.h> #include <errno.h> #include <soc_regs.h> #include "pwm_context.h" #include <drivers/cfg_drv/dev_config.h> #include <soc.h> #define LOG_LEVEL CONFIG_LOG_PWM_DEV_LEVEL #include <logging/log.h> LOG_MODULE_REGISTER(pwm); #define DMA_IRQ_TC (0) /* DMA completion flag */ #define DMA_IRQ_HF (1) /* DMA half-full flag */ enum PWM_GROUP { PWM_GROUP0_REG, PWM_GROUP1_REG, PWM_GROUP2_REG, PWM_GROUP3_REG, PWM_GROUP4_REG, PWM_GROUP5_REG, PWM_GROUP_MAX, }; #define PWM_FIFO_REG (6) #define PWM_IR_REG (7) #define PWM_INTCTL_REG (8) #define PWM_PENDING_REG (9) enum PWM_MODE { PWM_DEFAULT_REG, PWM_FIX_INIT, PWM_BTH_INIT, PWM_PRG_INIT, PWM_IR_INIT, PWM_MODE_MAX, }; #define PWM_MODE_MASK (0x7) #define PWM_chan(x) (1 << (3 + x)) #define PWM_chan_act(x) (1 << (9 + x)) #define PWM_chan_act_MASK (0x7e00) #define ir_code_pre_sym(a) ((a&0x8000) >> 15) #define ir_code_pre_val(a) ((a&0x7f00) >> 8) #define ir_code_pos_sym(a) ((a&0x80) >> 7) #define ir_code_pos_val(a) ((a&0x7f) >> 0) #define PWM_IR_REPEAT_MODE (0 << 8) #define PWM_IR_CYCLE_MODE (1 << 8) #define PWM_IR_MASK (0xff) #define PWM_IR_TX_MARGIN (1000) #define PWM_IR_TIMEOUT (1) /* IR_RX_ANA_CTL */ #define TX_ANA_EN (1) #define RX_ANA_CTL(base) (base + 0xf0) #define TX_ANA_CTL(base) (base + 0xf4) #define IR_TX_DINV (1 << 8) #define IR_TX_SR(X) (X << 4) #define IR_TX_POUT(X) (X << 1) #define IR_TX_EN (1) struct pwm_acts_data { struct k_sem dma_sync; struct k_sem ir_sync; struct k_sem ir_transfer_sync; struct device *dma_dev; int dma_chan; int (*program_callback)(void *cb_data, u8_t reason); void *cb_data; u8_t program_pin; u16_t group_init_status[6]; u32_t pwm_ir_sw; u32_t buf_num; u32_t pwm_ir_mode; struct k_timer timer; u32_t ir_event_timeout; u32_t pwm_ir_lc[2]; u32_t pwm_ir_ll[2]; u32_t pwm_ir_ld[2]; u32_t pwm_ir_pl[2]; u32_t pwm_ir_pd0[2]; u32_t pwm_ir_pd1[2]; u32_t pwm_ir_sl[2]; u8_t ir_pout; bool manual_stop_flag; }; struct pwm_acts_config { u32_t base; u32_t pwmclk_reg; u32_t cycle; u8_t clock_id; u8_t reset_id; const struct acts_pin_config *pinmux; u8_t pinmux_size; void (*irq_config_func)(void); const char *dma_dev_name; u8_t txdma_id; u8_t flag_use_dma; }; void pwm_acts_repeat_event_process(const struct pwm_acts_config *cfg, u32_t pending) { uint32_t pwm_base; if(pending & PWM_PENDING_G0REPEAT) { sys_write32(~(PWM_PENDING_G0REPEAT) & sys_read32(PWM_INT_CTL(cfg->base)), PWM_INT_CTL(cfg->base)); pwm_base = PWM0_BASE(cfg->base); struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)pwm_base; pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_CHx_MODE_SEL(0,0xfff)); } if(pending & PWM_PENDING_G1REPEAT) { sys_write32(~(PWM_PENDING_G1REPEAT) & sys_read32(PWM_INT_CTL(cfg->base)), PWM_INT_CTL(cfg->base)); pwm_base = PWM1_BASE(cfg->base); struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)pwm_base; pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_CHx_MODE_SEL(0,0xfff)); } if(pending & PWM_PENDING_G2REPEAT) { sys_write32(~(PWM_PENDING_G2REPEAT) & sys_read32(PWM_INT_CTL(cfg->base)), PWM_INT_CTL(cfg->base)); pwm_base = PWM2_BASE(cfg->base); struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)pwm_base; pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_CHx_MODE_SEL(0,0x3)); } if(pending & PWM_PENDING_G3REPEAT) { sys_write32(~(PWM_PENDING_G3REPEAT) & sys_read32(PWM_INT_CTL(cfg->base)), PWM_INT_CTL(cfg->base)); pwm_base = PWM3_BASE(cfg->base); struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)pwm_base; pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_CHx_MODE_SEL(0,0x3)); } if(pending & PWM_PENDING_G4REPEAT) { sys_write32(~(PWM_PENDING_G4REPEAT) & sys_read32(PWM_INT_CTL(cfg->base)), PWM_INT_CTL(cfg->base)); pwm_base = PWM4_BASE(cfg->base); struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)pwm_base; pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_CHx_MODE_SEL(0,0x3)); } } static void pwm_acts_ir_timeout_event(struct k_timer *timer) { struct pwm_acts_data *data = k_timer_user_data_get(timer); struct acts_pwm_ir *pwm_ir = (struct acts_pwm_ir *)PWM_IR(PWM_REG_BASE); pwm_ir->ir_ll = data->pwm_ir_ll[data->pwm_ir_sw]; pwm_ir->ir_ld = data->pwm_ir_ld[data->pwm_ir_sw]; pwm_ir->ir_pd0 = data->pwm_ir_pd0[data->pwm_ir_sw]; pwm_ir->ir_pd1 = data->pwm_ir_pd1[data->pwm_ir_sw]; pwm_ir->ir_sl = data->pwm_ir_sl[data->pwm_ir_sw]; pwm_ir->ir_pl = data->pwm_ir_pl[data->pwm_ir_sw]; pwm_ir->ir_lc = data->pwm_ir_lc[data->pwm_ir_sw]; pwm_ir->ir_ctl |= PWM_IRCTL_CU; if(data->pwm_ir_sw < data->buf_num) data->pwm_ir_sw++; if(data->pwm_ir_sw >= data->buf_num) { if(data->pwm_ir_mode & PWM_IR_CYCLE_MODE) data->pwm_ir_sw = 0; else data->pwm_ir_sw = data->buf_num -1; } k_timer_stop(&data->timer); } void pwm_acts_isr(void *arg) { struct device *dev = (struct device *)arg; struct pwm_acts_data *data = dev->data; const struct pwm_acts_config *cfg = dev->config; struct acts_pwm_ir *pwm_ir = (struct acts_pwm_ir *)PWM_IR(cfg->base); unsigned int key; key = irq_lock(); if((sys_read32(PWM_PENDING(cfg->base)) & PWM_PENDING_IRSS) && (data->buf_num > 1)) { pwm_ir->ir_ctl |= PWM_IRCTL_CU; u16_t timeout; timeout = (data->ir_event_timeout * pwm_ir->ir_ll)/1000 + PWM_IR_TIMEOUT; k_timer_start(&data->timer, K_MSEC(timeout), K_MSEC(timeout)); } irq_unlock(key); if(sys_read32(PWM_PENDING(cfg->base)) & PWM_PENDING_IRAE) { if (data->manual_stop_flag) { k_sem_give(&data->ir_sync); data->group_init_status[PWM_GROUP5_REG] = 0; } else { /* continue to send repeat code or data code */ pwm_ir->ir_ctl |= PWM_IRCTL_START; } } if(sys_read32(PWM_PENDING(cfg->base)) & (PWM_PENDING_REPEAT_MASK & sys_read32(PWM_INT_CTL(cfg->base)))) { pwm_acts_repeat_event_process(cfg, sys_read32(PWM_PENDING(cfg->base))); } sys_write32(0xffffffff, PWM_PENDING(cfg->base)); } static void pwm_acts_set_clk(const struct pwm_acts_config *cfg, uint32_t group, uint32_t freq_hz) { clk_set_rate(cfg->clock_id + group, freq_hz); k_busy_wait(100); } static u32_t pwm_acts_get_group(u32_t pwm) { u32_t group; if(pwm > 15) return -EINVAL; if((pwm) < 6) group = PWM_GROUP0_REG; else if((pwm) < 12) group = PWM_GROUP1_REG; else group = pwm -10; return group; } static u32_t pwm_acts_get_reg_base(u32_t base, uint32_t REG) { u32_t controller_reg; switch(REG) { case PWM_GROUP0_REG: controller_reg = PWM0_BASE(base); break; case PWM_GROUP1_REG: controller_reg = PWM1_BASE(base); break; case PWM_GROUP2_REG: controller_reg = PWM2_BASE(base); break; case PWM_GROUP3_REG: controller_reg = PWM3_BASE(base); break; case PWM_GROUP4_REG: controller_reg = PWM4_BASE(base); break; case PWM_GROUP5_REG: controller_reg = PWM5_BASE(base); break; case PWM_FIFO_REG: controller_reg = PWM_FIFO(base); break; case PWM_IR_REG: controller_reg = PWM_IR(base); break; case PWM_INTCTL_REG: controller_reg = PWM_INT_CTL(base); break; case PWM_PENDING_REG: controller_reg = PWM_PENDING(base); break; default: return -EINVAL; } return controller_reg; } /* * Set the period and pulse width for a PWM pin. * * Parameters * dev: Pointer to PWM device structure * pwm: PWM channel to set * period_cycles: Period (in timer count) * pulse_cycles: Pulse width (in timer count). * @param flags Flags for pin configuration (polarity). * return 0, or negative errno code */ static void pwm_acts_groupx_fix_init(u32_t base, u32_t period_cycles, u32_t pulse_cycles, u8_t chan, u8_t function, pwm_flags_t flags) { struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)base; u32_t pol_param; pwm->ctrl |= PWMx_CTRL_CHx_MODE_SEL(chan,1); if(chan < 4) { pol_param = PWMx_CH_CTL0_CHx_POL_SEL(chan); if(flags) pwm->ch_ctrl0 |= pol_param; else pwm->ch_ctrl0 = pwm->ch_ctrl0 & (~pol_param); } else { pol_param = PWMx_CH_CTL1_CHx_POL_SEL(chan); if(flags) pwm->ch_ctrl1 |= pol_param; else pwm->ch_ctrl1 = pwm->ch_ctrl1 & (~pol_param); } if(function) { pwm->cntmax = period_cycles; pwm->cmp[chan] = pulse_cycles; if((pwm->ctrl & PWMx_CTRL_HUA) == 0) pwm->ctrl |= PWMx_CTRL_HUA; else { k_usleep(30); pwm->ctrl |= PWMx_CTRL_HUA; } return; } pwm->cntmax = period_cycles; pwm->cmp[chan] = pulse_cycles; pwm->ctrl |= PWMx_CTRL_CNT_EN;//norlmal mode } static int pwm_acts_pin_set(const struct device *dev, uint32_t pwm, u32_t period_cycles, u32_t pulse_cycles, pwm_flags_t flags) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; uint32_t base,group; u16_t status; LOG_INF("PWM@%d set period cycles %d ms, pulse cycles %d ms", pwm, period_cycles, pulse_cycles); // period_cycles = period_cycles * pwm_normal_clk_rate / 1000; // pulse_cycles = pulse_cycles * pwm_normal_clk_rate / 1000; if (pulse_cycles > period_cycles) { LOG_ERR("pulse cycles %d is biger than period's %d", pulse_cycles, period_cycles); return -EINVAL; } group = pwm_acts_get_group(pwm); status = data->group_init_status[group]; if((status&PWM_MODE_MASK) != PWM_DEFAULT_REG && (status&PWM_MODE_MASK) != PWM_FIX_INIT) { LOG_ERR("start a fix mode but have not stop this group bfore!"); return -EINVAL; } pwm = (pwm > 5)?pwm-6:pwm; pwm = (pwm > 5)?pwm-4-group:pwm; base = pwm_acts_get_reg_base(cfg->base, group); if((status & PWM_chan(pwm)) == 0)//this group_chan have not initialized yet. pwm_acts_groupx_fix_init(base,period_cycles,pulse_cycles,pwm, 0, flags); else pwm_acts_groupx_fix_init(base,period_cycles,pulse_cycles,pwm, 1, flags); if(pulse_cycles == 0) { data->group_init_status[group] = data->group_init_status[group] & ~(PWM_chan_act(pwm)); } else { data->group_init_status[group] = PWM_FIX_INIT | PWM_chan(pwm) | status; data->group_init_status[group] |= PWM_chan_act(pwm); } return 0; } /* * Set the period and pulse width for a PWM pin. * * Parameters * dev: Pointer to PWM device structure * pwm: PWM channel to set * ctrl: breath mode control * return 0, or negative errno code */ #ifdef CONFIG_PWM_TAI_FULL_FUNC static void pwm_acts_groupx_breath_init(u32_t base, u8_t chan, pwm_breath_ctrl_t *ctrl) { struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)base; struct acts_pwm_breath_mode *breath = (struct acts_pwm_breath_mode *)(PWM_BREATH(base) + chan * PWM_BREATH_REG_SIZE); pwm->cntmax = ctrl->pwm_count_max; if(ctrl->stage_a_step) breath->pwm_bth_a = PWMx_BTHxy_EN | PWMx_BTHxy_XS(ctrl->stage_a_pwm) | PWMx_BTHxy_REPEAT(ctrl->stage_a_repeat) | PWMx_BTHxy_STEP(ctrl->stage_a_step); else breath->pwm_bth_a &= (~PWMx_BTHxy_EN); if(ctrl->stage_b_step) breath->pwm_bth_b = PWMx_BTHxy_EN | PWMx_BTHxy_XS(ctrl->stage_b_pwm) | PWMx_BTHxy_REPEAT(ctrl->stage_b_repeat) | PWMx_BTHxy_STEP(ctrl->stage_b_step); else breath->pwm_bth_b &= (~PWMx_BTHxy_EN); if(ctrl->stage_c_step) breath->pwm_bth_c = PWMx_BTHxy_EN | PWMx_BTHxy_XS(ctrl->stage_c_pwm) | PWMx_BTHxy_REPEAT(ctrl->stage_c_repeat) | PWMx_BTHxy_STEP(ctrl->stage_c_step); else breath->pwm_bth_c &= (~PWMx_BTHxy_EN); if(ctrl->stage_d_step) breath->pwm_bth_d = PWMx_BTHxy_EN | PWMx_BTHxy_XS(ctrl->stage_d_pwm) | PWMx_BTHxy_REPEAT(ctrl->stage_d_repeat) | PWMx_BTHxy_STEP(ctrl->stage_d_step); else breath->pwm_bth_d &= (~PWMx_BTHxy_EN); if(ctrl->stage_e_step) breath->pwm_bth_e = PWMx_BTHxy_EN | PWMx_BTHxy_XS(ctrl->stage_e_pwm) | PWMx_BTHxy_REPEAT(ctrl->stage_e_repeat) | PWMx_BTHxy_STEP(ctrl->stage_e_step); else breath->pwm_bth_e &= (~PWMx_BTHxy_EN); if(ctrl->stage_f_step) breath->pwm_bth_f = PWMx_BTHxy_EN | PWMx_BTHxy_XS(ctrl->stage_f_pwm) | PWMx_BTHxy_REPEAT(ctrl->stage_f_repeat) | PWMx_BTHxy_STEP(ctrl->stage_f_step); else breath->pwm_bth_f &= (~PWMx_BTHxy_EN); if(ctrl->stage_low_wait) breath->pwm_bth_hl = PWMx_BTHx_HL_L(ctrl->stage_low_wait) | PWMx_BTHx_HL_LEN; else breath->pwm_bth_hl &= (~PWMx_BTHx_HL_LEN); if(ctrl->stage_high_wait) breath->pwm_bth_hl = PWMx_BTHx_HL_H(ctrl->stage_high_wait) | PWMx_BTHx_HL_HEN; else breath->pwm_bth_hl &= (~PWMx_BTHx_HL_HEN); if(ctrl->start_dir) breath->pwm_bth_st = PWMx_BTHx_ST_ST(ctrl->start_pwm) | PWMx_BTHx_ST_DIR; else breath->pwm_bth_st = PWMx_BTHx_ST_ST(ctrl->start_pwm); pwm->ctrl |= PWMx_CTRL_CHx_MODE_SEL(chan,3) | PWMx_CTRL_CNT_EN;//breath mode } static int pwm_acts_set_breath_mode(const struct device *dev, uint32_t pwm, pwm_breath_ctrl_t *ctrl) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; uint32_t base,group; u16_t status; group = pwm_acts_get_group(pwm); status = data->group_init_status[group]; if((status&0x3) != PWM_BTH_INIT && (status&0x3)) {//not brearh mode or default LOG_ERR("start a breath mode but have not stop this group bfore!"); return -EINVAL; } pwm = (pwm > 5)?pwm-6:pwm; pwm = (pwm > 5)?pwm-4-group:pwm; base = pwm_acts_get_reg_base(cfg->base, group); if(group == PWM_GROUP1_REG || group == PWM_GROUP2_REG) pwm_acts_groupx_breath_init(base, pwm, ctrl); else { LOG_ERR("unsuported channel: %d",pwm); return -EINVAL; } data->group_init_status[group] = PWM_BTH_INIT | PWM_chan(pwm) | status; return 0; } #endif /* * Set the period and pulse width for a PWM pin. * * Parameters * dev: Pointer to PWM device structure * pwm: PWM channel to set * ctrl: program mode control * return 0, or negative errno code */ #ifdef CONFIG_PWM_TAI_FULL_FUNC static void dma_done_callback(const struct device *dev, void *callback_data, uint32_t ch , int type) { struct pwm_acts_data *data = (struct pwm_acts_data *)callback_data; //if (type != DMA_IRQ_TC) //return; LOG_DBG("pwm dma transfer is done"); k_sem_give(&data->dma_sync); } static int pwm_acts_start_dma(const struct pwm_acts_config *cfg, struct pwm_acts_data *data, uint32_t dma_chan, uint16_t *buf, int32_t len, bool is_tx, void *callback) { struct acts_pwm_fifo *pwm_fifo = (struct acts_pwm_fifo *)PWM_FIFO(cfg->base); struct dma_config dma_cfg = {0}; struct dma_block_config dma_block_cfg = {0}; if (callback) { dma_cfg.dma_callback = (dma_callback_t)callback; dma_cfg.user_data = data; dma_cfg.complete_callback_en = 1; } dma_cfg.block_count = 1; dma_cfg.head_block = &dma_block_cfg; dma_block_cfg.block_size = len; if (is_tx) { dma_cfg.dma_slot = cfg->txdma_id; dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL; dma_block_cfg.source_address = (uint32_t)buf; dma_block_cfg.dest_address = (uint32_t)&pwm_fifo->fifodat; dma_cfg.dest_data_size = 2; } else { return -EINVAL; } dma_cfg.source_burst_length = 4; if (dma_config(data->dma_dev, dma_chan, &dma_cfg)) { LOG_ERR("dma%d config error", dma_chan); return -1; } if (dma_start(data->dma_dev, dma_chan)) { LOG_ERR("dma%d start error", dma_chan); return -1; } return 0; } static void pwm_acts_stop_dma(const struct pwm_acts_config *cfg, struct pwm_acts_data *data, uint32_t dma_chan) { dma_stop(data->dma_dev, dma_chan); } static int pwm_acts_wait_fifo_staus(struct acts_pwm_fifo *pwm_fifo, uint16_t timeout) { int start_time; start_time = k_uptime_get_32(); while(!(pwm_fifo->fifosta&PWM_FIFOSTA_EMPTY)) { if(k_uptime_get_32() - start_time > 500) return 0; } return -EINVAL; } static int pwm_acts_dma_transfer(const struct pwm_acts_config *cfg, struct pwm_acts_data *data, u8_t chan, pwm_program_ctrl_t *ctrl) { struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)cfg->base; struct acts_pwm_fifo *pwm_fifo = (struct acts_pwm_fifo *)PWM_FIFO(cfg->base); int ret; pwm->ctrl |= PWMx_CTRL_CHx_MODE_SEL(chan,2) | PWMx_CTRL_CM | PWMx_CTRL_RM; if(ctrl->cntmax) { pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_CM); pwm->cntmax = ctrl->cntmax; } if(ctrl->repeat) { pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_RM); pwm->repeat = ctrl->repeat; } if(pwm_acts_wait_fifo_staus(pwm_fifo, 500)) { LOG_ERR("time out error, pwm fifo can not be empty!"); return -EINVAL; } pwm_fifo->fifoctl = PWM_FIFOCTL_START; ret = pwm_acts_start_dma(cfg, data, data->dma_chan, ctrl->ram_buf, ctrl->ram_buf_len, 1, dma_done_callback); if (ret) { LOG_ERR("faield to start dma chan 0x%x\n", data->dma_chan); goto out; } pwm->ctrl |= PWMx_CTRL_CNT_EN; /* wait until dma transfer is done */ k_sem_take(&data->dma_sync, K_FOREVER);//K_MSEC(500));// out: pwm_acts_stop_dma(cfg, data, data->dma_chan); if(pwm_acts_wait_fifo_staus(pwm_fifo, 500)) { LOG_ERR("time out error, pwm fifo can not be empty!"); return -EINVAL; } pwm->ctrl = pwm->ctrl & ~(PWMx_CTRL_CHx_MODE_SEL(chan,2) | PWMx_CTRL_CM | PWMx_CTRL_RM | PWMx_CTRL_CNT_EN); pwm_fifo->fifoctl = pwm_fifo->fifoctl & ~(PWM_FIFOCTL_START); return ret; } static int pwm_acts_set_program_mode(const struct device *dev, uint32_t pwm, pwm_program_ctrl_t *ctrl) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; uint32_t base,group; u16_t status; group = pwm_acts_get_group(pwm); status = data->group_init_status[group]; if((status&0x3) != PWM_PRG_INIT && (status&0x3)) {//not program mode or default LOG_ERR("start a breath mode but have not stop this group bfore!"); return -EINVAL; } pwm = (pwm > 5)?pwm-6:pwm; pwm = (pwm > 5)?pwm-4-group:pwm; base = pwm_acts_get_reg_base(cfg->base, group); if(group == PWM_GROUP0_REG || group == PWM_GROUP1_REG || group == PWM_GROUP2_REG) { pwm_acts_dma_transfer(cfg, data, pwm, ctrl);//这里有问题的需要修改,ctrl无法覆盖到group2和group1 } else { LOG_ERR("unsuported channel: %d",pwm); return -EINVAL; } // data->group_init_status[group] = PWM_BTH_INIT | PWM_chan(pwm) | status; return 0; } #endif //#define TX_ANA_CTL(base) (base + 0xf4) //#define IR_TX_DINV (1 << 8) //#define IR_TX_SR(X) (X << 4) //#define IR_TX_POUT(X) (X << 1) //#define IR_TX_EN (1) #if 0 static void pwm_acts_ir_reg_dump(struct acts_pwm_ir *pwm_ir) { printk("pwm_ir->ir_asc :%d\n", pwm_ir->ir_asc ); printk("pwm_ir->ir_duty :%d\n", pwm_ir->ir_duty ); printk("pwm_ir->ir_lc :%d\n", pwm_ir->ir_lc ); printk("pwm_ir->ir_ld :%d\n", pwm_ir->ir_ld ); printk("pwm_ir->ir_ll :%d\n", pwm_ir->ir_ll ); printk("pwm_ir->ir_pd0 :%d\n", pwm_ir->ir_pd0 ); printk("pwm_ir->ir_pd1 :%d\n", pwm_ir->ir_pd1 ); printk("pwm_ir->ir_period :%d\n", pwm_ir->ir_period ); printk("pwm_ir->ir_pl :%d\n", pwm_ir->ir_pl ); printk("pwm_ir->ir_pl0_post :%d\n", pwm_ir->ir_pl0_post ); printk("pwm_ir->ir_pl0_pre :%d\n", pwm_ir->ir_pl0_pre ); printk("pwm_ir->ir_pl1_post :%d\n", pwm_ir->ir_pl1_post ); printk("pwm_ir->ir_pl1_pre :%d\n", pwm_ir->ir_pl1_pre ); printk("pwm_ir->ir_sl :%d\n", pwm_ir->ir_sl ); } #endif static void pwm_acts_ir_tx(const struct pwm_acts_config *cfg, struct pwm_acts_data *data, u8_t chan, struct pwm_ir_mode_param_t *ctrl, uint32_t base) { struct acts_pwm_groupx *pwm = (struct acts_pwm_groupx *)base; struct acts_pwm_ir *pwm_ir = (struct acts_pwm_ir *)PWM_IR(cfg->base); u16_t mode; acts_pinmux_set(cfg->pinmux[cfg->pinmux_size - 1].pin_num, cfg->pinmux[cfg->pinmux_size - 1].mode); #if TX_ANA_EN sys_write32(0, RX_ANA_CTL(GPIO_REG_BASE)); sys_write32(IR_TX_EN | IR_TX_POUT(data->ir_pout), TX_ANA_CTL(GPIO_REG_BASE)); #endif while(pwm_ir->ir_ctl&PWM_IRCTL_START); data->pwm_ir_mode = ctrl[0].mode; mode = ctrl[0].mode & PWM_IR_MASK; pwm->ctrl |= PWMx_CTRL_CHx_MODE_SEL(chan,2); pwm_ir->ir_asc = ctrl[0].ir_asc; pwm_ir->ir_duty = ctrl[0].ir_duty; pwm_ir->ir_lc = ctrl[0].ir_lc; pwm_ir->ir_ld = ctrl[0].ir_ld; pwm_ir->ir_ll = ctrl[0].ir_ll; pwm_ir->ir_pd0 = ctrl[0].ir_pd0; pwm_ir->ir_pd1 = ctrl[0].ir_pd1; pwm_ir->ir_period = ctrl[0].ir_period; pwm_ir->ir_pl = ctrl[0].ir_pl; pwm_ir->ir_pl0_post = ctrl[0].ir_pl0_post; pwm_ir->ir_pl0_pre = ctrl[0].ir_pl0_pre; pwm_ir->ir_pl1_post = ctrl[0].ir_pl1_post; pwm_ir->ir_pl1_pre = ctrl[0].ir_pl1_pre; pwm_ir->ir_sl = ctrl[0].ir_sl; // pwm_acts_ir_reg_dump(pwm_ir); if(ctrl[0].buf_num > 1) { data->pwm_ir_sw = 1; data->pwm_ir_lc[0] = ctrl[0].ir_lc; data->pwm_ir_ld[0] = ctrl[0].ir_ld; data->pwm_ir_ll[0] = ctrl[0].ir_ll; data->pwm_ir_pd0[0] = ctrl[0].ir_pd0; data->pwm_ir_pd1[0] = ctrl[0].ir_pd1; data->pwm_ir_pl[0] = ctrl[0].ir_pl; data->pwm_ir_sl[0] = ctrl[0].ir_sl; data->pwm_ir_lc[1] = ctrl[1].ir_lc; data->pwm_ir_ld[1] = ctrl[1].ir_ld; data->pwm_ir_ll[1] = ctrl[1].ir_ll; data->pwm_ir_pd0[1] = ctrl[1].ir_pd0; data->pwm_ir_pd1[1] = ctrl[1].ir_pd1; data->pwm_ir_pl[1] = ctrl[1].ir_pl; data->pwm_ir_sl[1] = ctrl[1].ir_sl; } data->manual_stop_flag = false; data->buf_num = ctrl[0].buf_num; sys_write32(0xffffffff, PWM_PENDING(cfg->base)); sys_write32(PWM_INTCTL_IRAE | PWM_INTCTL_IRSS, PWM_INT_CTL(cfg->base)); pwm_ir->ir_ctl = PWM_IRCTL_PLED | PWM_IRCTL_START; pwm->ctrl |= PWMx_CTRL_CNT_EN; } static u32_t pwm_acts_data_cal(u32_t data, u32_t buf_num) { u32_t cal_val = 0; u32_t cal_dat = data; while(buf_num > 0) { if(cal_dat & 0x1) cal_val++; buf_num--; cal_dat = cal_dat >> 1; } return cal_val; } static u32_t pwm_acts_ir_get_len(u32_t ld) { u32_t len = 0; for(int i = 0; i < 32; i++) { if(ld & 0x80000000) break; len++; ld = ld << 1; } len = 32 - len; return len; } static void pwm_acts_ir_param_sw(struct ir_tx_data_param *ctrl, struct pwm_ir_mode_param_t *param, u32_t loc, struct ir_tx_protocol_param *protocol_param) { u32_t val, sym, ld_len, protocol; u16_t cr_rate; protocol = ctrl->mode; if(ctrl->rate) cr_rate = ctrl->rate/100; else cr_rate = protocol_param->ir_cr_rate; param->ir_period = pwm_clk_rate/(cr_rate * 1000); if(ctrl->duty) param->ir_duty = param->ir_period *10/ctrl->duty; else param->ir_duty = param->ir_period/3; param->ir_lc = cr_rate * protocol_param->ir_lc_bit_length/1000; sym = ir_code_pre_sym(protocol_param->ir_0_code) << 16; val = ir_code_pre_val(protocol_param->ir_0_code) * protocol_param->code_bit_length; val = val * cr_rate/1000; if(sym) val = val + 1;//process remainder param->ir_pl0_pre = sym | val; sym = ir_code_pos_sym(protocol_param->ir_0_code) << 16; val = ir_code_pos_val(protocol_param->ir_0_code) * protocol_param->code_bit_length; val = val * cr_rate/1000; if(sym) val = val + 1;//process remainder param->ir_pl0_post = sym | val; sym = ir_code_pre_sym(protocol_param->ir_1_code) << 16; val = ir_code_pre_val(protocol_param->ir_1_code) * protocol_param->code_bit_length; val = val * cr_rate/1000; if(sym) val = val + 1;//process remainder param->ir_pl1_pre = sym | val; sym = ir_code_pos_sym(protocol_param->ir_1_code) << 16; val = ir_code_pos_val(protocol_param->ir_1_code) * protocol_param->code_bit_length; val = val * cr_rate/1000; if(sym) val = val + 1;//process remainder param->ir_pl1_post = sym | val; param->ir_ll = pwm_acts_ir_get_len(protocol_param->ir_lc_code); param->ir_ld = protocol_param->ir_lc_code;//01b if(protocol & PWM_IR_CYCLE_MODE) { ld_len = pwm_acts_ir_get_len(protocol_param->ir_trc_loc); param->ir_pl = (loc == 1)?(protocol_param->ir_dc_length - ld_len):(ld_len -1); param->ir_asc = protocol_param->ir_asc; param->ir_Tf = (loc == 1)? 0 : (protocol_param->ir_Tf_length + PWM_IR_TX_MARGIN) * 10; val = ir_code_pos_val(protocol_param->ir_0_code) * protocol_param->code_bit_length; val = val * cr_rate/1000; if(protocol_param->ir_stop_bit && loc != 1) param->ir_lc = param->ir_lc - val; } else { param->ir_pl = protocol_param->ir_dc_length; param->ir_asc = protocol_param->ir_asc; param->ir_Tf = (protocol_param->ir_Tf_length + PWM_IR_TX_MARGIN) * 10; } param->ir_stop_bit = protocol_param->ir_stop_bit; } static void pwm_acts_ir_param_cal(struct ir_tx_data_param *ctrl, struct pwm_ir_mode_param_t *result, struct ir_tx_protocol_param *protocol_param) { u32_t num_0, num_1, sum_cycle, ir_sl, pwm_rate, mode, ld_len; u32_t data[2] = {0}; struct pwm_ir_mode_param_t param; mode = ctrl->mode & PWM_IR_MASK; pwm_acts_ir_param_sw(ctrl, &param , 1, protocol_param); pwm_rate = pwm_clk_rate/1000/param.ir_period; result[0].ir_period = param.ir_period; result[0].ir_duty = param.ir_duty; result[0].ir_lc = param.ir_lc; result[0].ir_pl0_pre = param.ir_pl0_pre; result[0].ir_pl0_post = param.ir_pl0_post; result[0].ir_pl1_pre = param.ir_pl1_pre; result[0].ir_pl1_post = param.ir_pl1_post; result[0].ir_ll = param.ir_ll; result[0].ir_ld = param.ir_ld;//01b if(param.ir_stop_bit) { param.ir_pl = param.ir_pl + 1;//patload 24bit+endflag ctrl->data[1] = (ctrl->data[1] << 1) | (ctrl->data[0] >> 31); ctrl->data[0] = ctrl->data[0] << 1; } ld_len = pwm_acts_ir_get_len(protocol_param->ir_trc_loc); data[0] = ctrl->data[0] >> ld_len; data[1] = ctrl->data[1] >> ld_len; result[0].ir_pl = param.ir_pl; if(param.ir_pl > 32) { result[0].ir_pd0 = data[0]; num_1 = pwm_acts_data_cal(data[0], 32); result[0].ir_pd1 = data[1]; num_1 += pwm_acts_data_cal(data[0], result[0].ir_pl - 32); } else { result[0].ir_pd0 = data[0]; num_1 = pwm_acts_data_cal(data[0], result[0].ir_pl); } num_0 = result[0].ir_pl - num_1; sum_cycle = result[0].ir_lc*result[0].ir_ll; sum_cycle += num_0*((result[0].ir_pl0_pre&0xff) + (result[0].ir_pl0_post&0xff)); sum_cycle += num_1*((result[0].ir_pl1_pre&0xff) + (result[0].ir_pl1_post&0xff)); if(param.ir_Tf) { ir_sl = (param.ir_Tf/1000 - (sum_cycle/pwm_rate)); ir_sl = ir_sl * pwm_rate / result[0].ir_lc; result[0].ir_sl = ir_sl; } else result[0].ir_sl = 0; if(ctrl->buf_num > 1 && (ctrl->mode & PWM_IR_CYCLE_MODE)) result[0].ir_asc = param.ir_asc * 2; else if(ctrl->buf_num > 1) result[0].ir_asc = param.ir_asc + 1; else result[0].ir_asc = param.ir_asc; if(ctrl->buf_num > 1) { if(ctrl->mode & PWM_IR_CYCLE_MODE) pwm_acts_ir_param_sw(ctrl, &param, 2, protocol_param); else pwm_acts_ir_param_sw(ctrl, &param, 2, protocol_param + 1); result[1].ir_lc = param.ir_lc; if(ctrl->lead == NULL) { result[1].ir_ld = param.ir_ld; result[1].ir_ll = param.ir_ll; } else { result[1].ir_ld = ctrl->lead->ld; result[1].ir_ll = ctrl->lead->ll; } if(param.ir_stop_bit) param.ir_pl = param.ir_pl + 1;//patload 24bit+endflag result[1].ir_pl = param.ir_pl; data[0] = data[1] = 0; ld_len = (1 << ld_len) - 1; data[0] = ctrl->data[0] & ld_len; data[1] = ctrl->data[1] & ld_len; if(param.ir_pl > 32) { result[1].ir_pd0 = data[0]; num_1 = pwm_acts_data_cal(data[0], 32); result[1].ir_pd1 = data[1]; num_1 += pwm_acts_data_cal(data[0], result[1].ir_pl - 32); } else { result[1].ir_pd0 = data[0]; num_1 = pwm_acts_data_cal(data[0], result[1].ir_pl); } result[1].ir_sl = 0; num_0 = result[1].ir_pl - num_1; if(ctrl->mode & PWM_IR_CYCLE_MODE) sum_cycle += param.ir_lc * result[1].ir_ll; else sum_cycle = param.ir_lc * result[1].ir_ll; sum_cycle += num_0*((param.ir_pl0_pre&0xff) + (param.ir_pl0_post&0xff)); sum_cycle += num_1*((param.ir_pl1_pre&0xff) + (param.ir_pl1_post&0xff)); if(param.ir_Tf) { ir_sl = (param.ir_Tf/1000 - (sum_cycle/pwm_rate)); ir_sl = ir_sl * pwm_rate / param.ir_lc; result[1].ir_sl = ir_sl; } } result[0].buf_num = ctrl->buf_num; result[0].mode = ctrl->mode; } static int pwm_acts_ir_transfer(const struct device *dev, u32_t pwm, pwm_ir_ctrl_t *ctrl) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; uint32_t base, group; u16_t status; struct pwm_ir_mode_param_t result[2] = {0}; struct ir_tx_protocol_param *ir_protocol = ctrl->protocol; struct ir_tx_data_param *ir_data = ctrl->data; k_sem_take(&data->ir_transfer_sync, K_FOREVER); data->ir_event_timeout = ir_protocol->ir_lc_bit_length; pwm_acts_ir_param_cal(ir_data, result, ir_protocol); group = pwm_acts_get_group(pwm); status = data->group_init_status[group]; if((status&PWM_MODE_MASK) != PWM_IR_INIT && (status&PWM_MODE_MASK) != PWM_DEFAULT_REG) {//not ir mode or default LOG_ERR("start a ir mode but have not stop this group bfore!"); return -EINVAL; } pwm = (pwm > 5)?pwm-6:pwm; pwm = (pwm > 5)?pwm-4-group:pwm; base = pwm_acts_get_reg_base(cfg->base, group); if(group == PWM_GROUP5_REG) {//only group 5 support ir pwm_acts_ir_tx(cfg, data, pwm, result, base); } else { LOG_ERR("unsuported channel: %d",pwm); return -EINVAL; } data->group_init_status[group] = PWM_IR_INIT | PWM_chan(pwm) | status; return 0; } static int pwm_acts_ir_stop_transfer(const struct device *dev) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; struct acts_pwm_ir *pwm_ir = (struct acts_pwm_ir *)PWM_IR(cfg->base); if (pwm_ir->ir_ctl & PWM_IRCTL_START) { data->manual_stop_flag = true; pwm_ir->ir_ctl |= PWM_IRCTL_STOP; } k_sem_take(&data->ir_sync, K_FOREVER); k_sem_give(&data->ir_transfer_sync); return 0; } #ifdef CONFIG_PWM_TAI_FULL_FUNC static int pwm_acts_pin_stop(const struct device *dev, uint32_t pwm) { return 0; } #endif static int pwm_acts_pin_repeat(const struct device *dev, uint32_t pwm, uint8_t repeat) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; uint32_t base,group; u16_t status; unsigned int key; if(repeat == 0) return -EINVAL; key = irq_lock(); group = pwm_acts_get_group(pwm); status = data->group_init_status[group]; pwm = (pwm > 5)?pwm-6:pwm; pwm = (pwm > 5)?pwm-4-group:pwm; base = pwm_acts_get_reg_base(cfg->base, group); switch(group){ case PWM_GROUP0_REG: sys_write32(PWM_INTCTL_G0REPEAT, PWM_INT_CTL(cfg->base)); break; case PWM_GROUP1_REG: sys_write32(PWM_INTCTL_G1REPEAT, PWM_INT_CTL(cfg->base)); break; case PWM_GROUP2_REG: sys_write32(PWM_INTCTL_G2C0 | PWM_INTCTL_G2REPEAT, PWM_INT_CTL(cfg->base)); break; case PWM_GROUP3_REG: sys_write32(PWM_INTCTL_G3C0 | PWM_INTCTL_G3REPEAT, PWM_INT_CTL(cfg->base)); break; case PWM_GROUP4_REG: sys_write32(PWM_INTCTL_G4C0 | PWM_INTCTL_G4REPEAT, PWM_INT_CTL(cfg->base)); break; case PWM_GROUP5_REG: sys_write32(PWM_INTCTL_G5C0 | PWM_INTCTL_G5REPEAT, PWM_INT_CTL(cfg->base)); break; default: return -EINVAL; } struct acts_pwm_groupx *pwm_reg = (struct acts_pwm_groupx *)base; pwm_reg->repeat = repeat; pwm_reg->ctrl |= PWMx_CTRL_HUA; // k_sleep(K_USEC(32)); // pwm_reg->ctrl |= PWMx_CTRL_CU; sys_write32(0xffffffff, PWM_PENDING(cfg->base)); irq_unlock(key); return 0; } /* * Get the clock rate (cycles per second) for a PWM pin. * * Parameters * dev: Pointer to PWM device structure * pwm: PWM port number * cycles: Pointer to the memory to store clock rate (cycles per second) * * return 0, or negative errno code */ #ifdef CONFIG_PWM_TAI_FULL_FUNC static int pwm_acts_get_cycles_per_sec(const struct device *dev, uint32_t pwm, u64_t *cycles) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; u32_t group; group = pwm_acts_get_group(pwm); if(group == PWM_GROUP5_REG) *cycles = pwm_clk_rate; else *cycles = pwm_normal_clk_rate; return 0; } #endif static int pwm_acts_reset_peripheral(int reset_id) { sys_write32((sys_read32(RMU_MRCR0) & ~(0x3f << reset_id)), RMU_MRCR0); sys_write32(((0x3f << reset_id) | sys_read32(RMU_MRCR0)), RMU_MRCR0); return 0; } static int pwm_acts_ir_tx_power(const struct device *dev, uint8_t level) { struct pwm_acts_data *data = dev->data; if(level > 7) { LOG_ERR("error param level:%d", level); return -1; } data->ir_pout = level; return 0; } int pwm_acts_init(const struct device *dev) { const struct pwm_acts_config *cfg = dev->config; struct pwm_acts_data *data = dev->data; acts_pinmux_setup_pins(cfg->pinmux, cfg->pinmux_size - 1); /* reset pwm controller */ pwm_acts_reset_peripheral(cfg->reset_id); cfg->irq_config_func(); for(int i = 0;i < 5;i++) { /* enable pwm controller clock */ acts_clock_peripheral_enable(cfg->clock_id + i); /* 32kHZ */ pwm_acts_set_clk(cfg, i, pwm_normal_clk_rate); } acts_clock_peripheral_enable(cfg->clock_id + 5); pwm_acts_set_clk(cfg, 5, pwm_clk_rate);//pwm_normal_clk_rate);// memset(data->group_init_status, 0 ,6); k_sem_init(&data->ir_sync, 0, 1); k_sem_init(&data->ir_transfer_sync, 0, 1); k_sem_give(&data->ir_transfer_sync); if (cfg->dma_dev_name != NULL) { data->dma_dev = (struct device *)device_get_binding(cfg->dma_dev_name); if (!data->dma_dev) { LOG_ERR("Bind DMA device %s error", cfg->dma_dev_name); return -ENOENT; } k_sem_init(&data->dma_sync, 0, 1); data->dma_chan = dma_request(data->dma_dev, 0xff); if(data->dma_chan < 0){ LOG_ERR("dma-dev rxchan config err chan=%d\n", data->dma_chan); return -ENODEV; } } data->ir_pout = 0; data->manual_stop_flag = false; k_timer_init(&data->timer, pwm_acts_ir_timeout_event, NULL); k_timer_user_data_set(&data->timer, (void *)data); return 0; } const struct pwm_driver_api pwm_acts_driver_api = { .pin_set = pwm_acts_pin_set, .ir_transfer = pwm_acts_ir_transfer, .ir_stop_transfer = pwm_acts_ir_stop_transfer, .pin_repeat = pwm_acts_pin_repeat, .ir_tx_power_set = pwm_acts_ir_tx_power, #ifdef CONFIG_PWM_TAI_FULL_FUNC .get_cycles_per_sec = pwm_acts_get_cycles_per_sec, .set_breath = pwm_acts_set_breath_mode, .set_program = pwm_acts_set_program_mode, .pin_stop = pwm_acts_pin_stop, #endif }; static struct pwm_acts_data pwm_acts_data; static const struct acts_pin_config pins_pwm[] = {CONFIG_PWM_MFP}; static void pwm_acts_irq_config(void); static const struct pwm_acts_config pwm_acts_config = { .base = PWM_REG_BASE, .cycle = CONFIG_PWM_CYCLE, .clock_id = CLOCK_ID_PWM0, .reset_id = RESET_ID_PWM0, .dma_dev_name = CONFIG_DMA_0_NAME, .txdma_id = CONFIG_PWM_DMA_ID, .pinmux = pins_pwm, .irq_config_func = pwm_acts_irq_config, .pinmux_size = ARRAY_SIZE(pins_pwm), }; #if CONFIG_PWM static void pwm_acts_pinmux_setup_pins(const struct acts_pin_config *pinconf, int pins, u8_t flag) { int i; for (i = 0; i < pins; i++) { if(flag) acts_pinmux_set(pinconf[i].pin_num, pinconf[i].mode); else acts_pinmux_set(pinconf[i].pin_num, 0x1000); } } static int pwm_acts_active(const struct device *dev) { const struct pwm_acts_config *cfg = dev->config; pwm_acts_pinmux_setup_pins(cfg->pinmux, cfg->pinmux_size - 1, 1); pwm_acts_reset_peripheral(cfg->reset_id); cfg->irq_config_func(); for(int i = 0;i < 5;i++) { acts_clock_peripheral_enable(cfg->clock_id + i); pwm_acts_set_clk(cfg, i, pwm_normal_clk_rate); } acts_clock_peripheral_enable(cfg->clock_id + 5); pwm_acts_set_clk(cfg, 5, pwm_clk_rate);//pwm_normal_clk_rate);// return 0; } static int pwm_acts_suspend(const struct device *dev) { struct pwm_acts_data *data = dev->data; const struct pwm_acts_config *cfg = dev->config; u16_t status; for(int i = 0; i < PWM_GROUP_MAX; i++) { status = data->group_init_status[i] & PWM_MODE_MASK; if((status != PWM_DEFAULT_REG) &&(status != PWM_FIX_INIT)) { return -ESRCH; } status = data->group_init_status[i]; if((PWM_FIX_INIT == (status & PWM_MODE_MASK)) && ((status & PWM_chan_act_MASK) != 0)) { return -ESRCH; } } pwm_acts_pinmux_setup_pins(cfg->pinmux, cfg->pinmux_size, 0); memset(data->group_init_status, 0 ,6); sys_write32((sys_read32(RMU_MRCR0) & ~(0x3f << cfg->reset_id)), RMU_MRCR0); for(int i = 0; i < PWM_GROUP_MAX; i++) acts_clock_peripheral_disable(cfg->clock_id + i); return 0; } static int pwm_acts_pm_control(const struct device *dev, uint32_t command, void *context, device_pm_cb cb, void *arg) { int ret = 0; uint32_t state = *((uint32_t*)context); static u8_t sleep_status = 1; LOG_DBG("command:0x%x state:%d", command, state); if (command != DEVICE_PM_SET_POWER_STATE) return 0; switch (state) { case DEVICE_PM_ACTIVE_STATE: if(sleep_status == 0) pwm_acts_active(dev); sleep_status = 1; break; case DEVICE_PM_SUSPEND_STATE: ret = pwm_acts_suspend(dev); if(ret == 0) sleep_status = 0; break; case DEVICE_PM_EARLY_SUSPEND_STATE: case DEVICE_PM_LATE_RESUME_STATE: case DEVICE_PM_LOW_POWER_STATE: case DEVICE_PM_OFF_STATE: break; default: ret = -ESRCH; } return ret; } DEVICE_DEFINE(pwm_acts, CONFIG_PWM_NAME, pwm_acts_init, pwm_acts_pm_control, &pwm_acts_data, &pwm_acts_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &pwm_acts_driver_api); static void pwm_acts_irq_config(void) { IRQ_CONNECT(IRQ_ID_PWM, CONFIG_PWM_IRQ_PRI, pwm_acts_isr, DEVICE_GET(pwm_acts), 0); irq_enable(IRQ_ID_PWM); //IRQ_CONNECT(IRQ_ID_KEY_WAKEUP, 1, // mxkeypad_acts_wakeup_isr, DEVICE_GET(mxkeypad_acts), 0); } #endif 请记住以上代码内容
06-24
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