Always if2

原创于 2022-03-10 19:44:23 发布 · 423 阅读

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#verilog

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这篇博客探讨了在硬件描述语言中如何通过条件赋值避免产生锁存器，例如在`top_module`中，根据`cpu_overheated`和`(~arrived & ~gas_tank_empty)`的状态来智能地控制`shut_off_computer`和`keep_driving`的输出。

避免产生锁存器

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); 

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived && ~gas_tank_empty)
           keep_driving = 1;
        else 
            keep_driving <= 0;
    end

endmodule