FPGA Block RAM自动推断

本文探讨了Xilinx 7系列和UltraScale+ FPGA中Block RAM的配置方式,强调18Kb和36Kb作为基本单元。通过设计RTL代码,可以自动推断使用18Kb/36Kb单元,实现跨平台兼容性。实验验证了不同配置下的Block RAM使用情况,如单端口、简单双端口和真双端口RAM,以及字和字节操作。此外,还比较了Block RAM型FIFO与内置FIFO的区别,并提出了Block RAM的最佳使用建议。

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#FPGA Block RAM自动推断

首先看一下摘自UG的资料:

  • Xilinx 7 series
  • The block RAM in Xilinx@ 7 series FPGAs stores up to 36 Kbits of data and can be
    configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block
    RAM can be configured as a 64K x 1 (when cascaded with an adjacent 36 Kb block RAM),
    32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18, 1K x 36, or 512 x 72 in simple dual-port mode.
    Each 18 Kb block RAM can be configured as a 16K x 1, 8K x2 , 4K x 4, 2K x 9, 1K x 18 or
    512 x 36 in simple dual-port mode.
  • 18, 36, or 72-bit wide block RAM ports can have an individual write enable per byte.
    This feature is popular for interfacing to a microprocessor.
  • Xilinx ultrascale+
  • The block RAM in UltraScale architecture-based devices stores up to 36 Kbits of data and
    can be configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each
    block RAM has two write and two read ports. A 36 Kb block RAM can be configured with
    independent port widths for each of those ports as 32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18
    or 1K x 36 (when used as true dual-port (TDP) memory). If only one write and one read port
    are used, a 36 Kb block RAM can additionally be configured with a port width of 512 x 72
    bits (when used as simple dual-port (SDP) memory). An 18 Kb block RAM can be configured
    with independent port widths for each of those ports as 16K x 1, 8K x 2, 4K x 4, 2K x 9 or
    1K x 18 (when used as T DP memory). If only one write and one read port are used, an 18 Kb
    block RAM can additionally be configured with a port width of 512 x 36 bits (when used as
    SDP memory).
  • The RAM MODE attribute has been removed. The Vivado@ tools automatically
    determine if a block RAM is used in TDP or SDP m
### 内置FIFO与Block RAM的硬件设计及FPGA实现差异 #### 功能定义 内置FIFO(First-In-First-Out)是一种数据缓冲结构,主要用于处理不同速率的数据流传输。它通过存储和释放数据来平衡输入输出速度差[^2]。而Block RAMFPGA中的专用存储模块,通常用于实现各种类型的内存功能,如单端口RAM、双端口RAM以及ROM等。 #### 资源利用 Block RAMFPGA中是一个固定的硬件资源,其容量和性能由具体器件决定。当使用Block RAM作为存储单元时,可以自动推断出所需的RAM配置,例如深度、宽度和其他参数[^1]。然而,对于内置FIFO来说,由于其实现机制较为复杂,并且涉及额外的功能控制逻辑(如满信号、空信号),因此无法完全依赖综合工具进行自动推断,需手动实例化IP核或调用库函数完成设计。 #### 性能对比 从延迟角度来看,简单的Block RAM读写操作具有较低延时特性,适合于那些对时间敏感的应用场景。相比之下,虽然内置FIFO也提供了快速访问能力,但由于增加了状态管理电路等因素影响,整体可能会稍逊一筹。另外,在某些特定条件下比如浅度高带宽需求下,移位寄存器形式的FIFO可能被采用,但这会消耗较多LUT资源而非专门针对优化过的BRAM单元。 #### 配置灵活性 就可配置选项而言,两者各有千秋。Block RAM允许灵活调整字长(bit/byte level),并推荐采用双端口模式以提高吞吐量;而对于标准型式的Built-in FIFO组件,则预先设定了多种常用规格供开发者选用,简化了定制过程的同时牺牲了一定程度上的自由度。 ```python # Example of instantiating a built-in FIFO using XPM library in VHDL library ieee; use ieee.std_logic_1164.all; entity fifo_example is port ( rst : in std_logic; -- Reset signal wr_clk : in std_logic; -- Write clock rd_clk : in std_logic; -- Read clock din : in std_logic_vector(7 downto 0); -- Data input wr_en : in std_logic; -- Write enable rd_en : in std_logic; -- Read enable dout : out std_logic_vector(7 downto 0); -- Data output full : out std_logic; -- Full flag empty : out std_logic -- Empty flag ); end entity fifo_example; architecture rtl of fifo_example is begin your_fifo_instance_name : YOUR_FIFO_COMPONENT_NAME generic map( -- Map generics here as needed based on component requirements. ) port map ( -- Port mappings go here according to the instantiated IP core ports. ); end architecture rtl; ``` 上述代码片段展示了如何基于Xilinx Parameterized Macro (XPM) 库创建一个VHDL版本的基本FIFO实体声明及其架构描述部分框架示意。
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