The Physical Address Extension (PAE) Paging Mechanism

The amount of RAM supported by a processor is limited by the number of address pins connected to the address bus.

PAE is activated by setting the Physical Address Extension ( PAE ) flag in the cr4 control register. The Page Size ( PS ) flag in the page directory entry enables large page sizes (2 MB when PAE is enabled).

When mapping linear addresses to 4 KB pages ( PS flag cleared in Page Directory entry), the 32 bits of a linear address are interpreted in the following way:

cr3

        Points to a PDPT

bits 31–30

        Point to 1 of 4 possible entries in PDPT

bits 29–21

        Point to 1 of 512 possible entries in Page Directory

bits 20–12

        Point to 1 of 512 possible entries in Page Table

bits 11–0

        Offset of 4-KB page

When mapping linear addresses to 2-MB pages ( PS flag set in Page Directory entry), the 32 bits of a linear address are interpreted in the following way:

cr3
        Points to a PDPT
bits 31–30
       Point to 1 of 4 possible entries in PDPT
bits 29–21
       Point to 1 of 512 possible entries in Page Directory
bits 20–0
       Offset of 2-MB page

To summarize, once cr3 is set, it is possible to address up to 4 GB of RAM. If we want to address more RAM, we’ll have to put a new value in cr3 or change the content of the PDPT.

Clearly, PAE does not enlarge the linear address space of a process, because it deals only with physical addresses. Furthermore, only the kernel can modify the page tables of the processes, thus a process running in User Mode cannot use a physical address space larger than 4 GB.

Note: For linear address, only the last 12-bit offset are the size of the page frame. Other fields are the numbers of the corresponding entries in the table. When the base address pointer plug the number, it will get be 'base address + number * 4(or 8) = the entry address'.