ISim P.20131013 (signature 0x7708f090)

ISim P.20131013 (signature 0x7708f090)
This is a Full version of ISim.
WARNING: File "F:/workspace/FPGA/xilinx/DDR3/tsb.v" Line 35. For instance tsb/uut/, width 12 of formal port sys_addr is not equal to width 16 of actual variable sys_addr.
WARNING: File "F:/workspace/FPGA/xilinx/DDR3/tsb.v" Line 41. For instance tsb/uut/, width 14 of formal port mcb5_dram_a is not equal to width 13 of actual signal mcb5_dram_a.
WARNING: File "F:/workspace/FPGA/xilinx/DDR3/tsb.v" Line 53. For instance tsb/uut/, width 14 of formal port mcb1_dram_a is not equal to width 13 of actual signal mcb1_dram_a.
Time resolution is 1 ps
Simulator is doing circuit initialization process.
ERROR: In process DDR_WR_FSM.vCont_96_11
FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/