Latch Levels

本文深入探讨了Oracle数据库中latch机制的工作原理及如何通过latch级别控制来避免死锁现象,详细解释了latch的级别规定、获取方式以及Oracle如何确保多个latch间的正确顺序获取。
 
 
Steve Adams的书中的latch levels提到:
It is very common for an Oracle process to need to hold a number of latches
concurrently. Therefore, there might be a possibility of latching deadlocks
occurring—namely, one process holding latch A and another process holding
latch B, and both processes spinning and waiting for the alternate latch. Oracle
ensures that this cannot happen by ensuring that latches are always taken in a
defined order, when more than one latch is required. To support this, every latch
in Oracle has a level between and 15, and a 2-byte bitmap is maintained for every
process representing the levels of the latches that the process is currently holding.
When a process attempts to get a latch in willing-to-wait mode, a check is made
to ensure that it is not already holding a latch at the same level or at a higher
level. In general, if this rule is broken, an ORA-600 [504] internal error is
raised.

Contention for a high-level latch such as the redo allocation latch (level 6) can
easily exacerbate contention for lower-level latches such as the cache buffers
chains latches (level 1 in Oracle 8.1).
 
 
level的规定,实际上是对进程获得latch进行了序列化、串行化控制。

简单地使用level 来控制(争用相对少,这样实现简单、成本低,如果采用 lock 机制那成本太高了),避免 dead lock。

来自 “ ITPUB博客 ” ,链接:http://blog.itpub.net/13750068/viewspace-731425/,如需转载,请注明出处,否则将追究法律责任。

转载于:http://blog.itpub.net/13750068/viewspace-731425/

翻译:The MAX3224E–MAX3227E/MAX3244E/MAX3245E achieve a 1μA supply current with Maxim’s AutoShutdown Plus feature, which operates when FORCEOFF is high and a FORCEON is low. When these devices do not sense a valid signal transition on any receiver and transmitter input for 30s, the on-board charge pumps are shut down, reducing supply current to 1μA. This occurs if the RS-232 cable is disconnected or if the connected peripheral transmitters are turned off, and the UART driving the transmitter inputs is inactive. The system turns on again when a valid transition is applied to any RS-232 receiver or transmitter input. As a result, the system saves power without changes to the existing BIOS or operating system. Figures 3a and 3b depict valid and invalid RS-232 receiver voltage levels. INVALID indicates the receiver input’s condition, and is independent of FORCEON and FORCEOFF states. Figure 3 and Tables 1 and 2 summarize the operating modes of the MAX3224E–MAX3227E/ MAX3244E/MAX3245E. FORCEON and FORCEOFF override AutoShutdown Plus circuitry. When neither control is asserted, the IC selects between these states automatically based on the last receiver or transmitter input edge received When shut down, the device’s charge pumps turn off, V+ is pulled to VCC, V- is pulled to ground, the transmitter outputs are high impedance, and READY (MAX3224E– MAX3227E) is driven low. The time required to exit shutdown is typically 100μs (Figure 8). By connecting FORCEON to INVALID, the MAX3224E– MAX3227E/MAX3244E/MAX3245E shut down when no valid receiver level and no receiver or transmitter edge is detected for 30s, and wake up when a valid receiver level or receiver or transmitter edge is detected.By connecting FORCEON and FORCEOFF to INVALID, the MAX3224E–MAX3227E/MAX3244E/MAX3245E shut down when no valid receiver level is detected and wake up when a valid receiver level is detected (same functionality as AutoShutdown feature on MAX3221E/MAX3223E/ MAX3243E). A mouse or other system with AutoShutdown Plus may need time to wake up. Figure 5 shows a circuit that forces the transmitters on for 100ms, allowing enough time for the other system to realize that the MAX3244E/ MAX3245E is awake. If the other system outputs valid RS-232 signal transitions within that time, the RS-232 ports on both systems remain enabled. Software-Controlled Shutdown If direct software control is desired, use INVALID to indicate DTR or ring indicator signal. Tie FORCEOFF and FORCEON together to bypass the AutoShutdown Plus so the line acts like a SHDN input. ±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX3224E– MAX3227E/MAX3244E/MAX3245E have extra protection against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, Maxim’s E versions keep working without latchup, whereas competing RS-232 products can latch and must be powered down to remove latchup. ESD protection can be tested in various ways; the transmitter outputs and receiver inputs of this product family are characterized for protection to the following limits: 1) ±15kV using the Human Body Model 2) ±8kV using the Contact-Discharge Method specified in IEC 1000-4-2 3) ±15kV using IEC 1000-4-2’s Air-Gap Method.
08-21
6.2 Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q256JV provides several means to protect the data from inadvertent writes.  Device resets when VCC is below threshold  Time delay write disable after Power-up  Write enable/disable instructions and automatic write disable after erase or program  Software and Hardware (/WP pin) write protection using Status Registers  Additional Individual Block/Sector Locks for array protection  Write Protection using Power-down instruction  Lock Down write protection for Status Register until the next power-up  One Time Program (OTP) write protection for array and Security Registers using Status Register* * Note: This feature is available upon special flow. Please contact Winbond for details. Upon power-up or at power-down, the W25Q256JV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at powerdown to prevent adverse command sequence. If needed, a pull-up resistor on /CS pin can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. The W25Q256JV also provides another Write Protect method using the Individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block. The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When WPS=0 (factory default), the device will only utilize CMP, TB, BP[3:0] bits to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
10-14
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