Quartus中仿真时出现no simulation input file assignment specify

最新推荐文章于 2022-09-05 16:06:26 发布
原创 最新推荐文章于 2022-09-05 16:06:26 发布 · 2.7w 阅读 · 40 ·
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本文详细解释了在FPGA开发过程中遇到的仿真文件未指定错误的原因及解决步骤，包括如何创建仿真文件、添加输入输出端口、设置信号、保存文件以及正确进行功能仿真。确保在进行FPGA仿真前正确配置仿真环境，避免因未指定仿真文件而导致的错误。

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最近学习FPGA，今天出现了一个错误提示：no simulation input file assignment specify ...以前没遇到过的

  具体过程是这样的，今天试验在各个工程文件中生成功能模块，然后新建一个工程，调用各个模块，导致进行仿真时提示了那个错误。然后百度了下，确实有些问题：

翻译成中文就是仿真文件没有被指定，要仿真的话先要建一个仿真文件: file -> new -> 选择Other file选项卡 -> Vector Waveform File 。  然后把输入输出端口加进去，再设置输入的信号，保存，就可以仿真了。

如果你之前已经建立过了，就打开assignments->settings->simulator settings

看里面的有个文本框 simulation input 里面是否为空，为空的话就要找到你所建立的Vector Waveform File 文件，是以*.VMF结尾的，如果没找到，你又以为你建立了Vector Waveform File ,很可能粗心的你还没保存Vector Waveform File ,保存了才会在project里面找到。

找到之后进行仿真，如果是functional simulation，要做processing>generate functional simulation netlist..不然会出现

Error: Run Generate Functional Simulation Netlist (quartus_map bmg_control --generate_functional_sim_netlist) to generate functional simulation netlist for top level entity bmg_control before running the Simulator (quartus_sim)之类的错误。最后在进行仿真，就可以看到波形图了。

Quartus中仿真时出现no simulation input file assignment specify 解决方法 (转载)
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今天使用quartusII做了一下功能仿真，但是文件出现了问题 Error: Run Generate Functional Simulation Netlist (。。。) to generate functional simulation netlist for top level entity bmg_control before running the Simulator (...
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QuartusII中仿真时出现No simulation input file assignment specified on simulator page of the settings dialog box解决方法   翻译成中文：仿真文件没有被指定，要仿真的话先要建一个仿真文件；  情况一：（你没有建过仿真文件）file -> new -> 选择Other file选项卡 -> Ve
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使用QuartusII仿真时出现No simulation input file assignment specified on simulator page of the settings dialog box的解决方法 没有建立仿真文件。file->new->Vector Waveform File添加一个文件，写入输入输出端口，设置输入信号，保存并Add file to cur...
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一.点击File,点击new， 点击上图的蓝色部分，然后一直OK，出现如下界面 然后执行【File\Save As …】菜单命令，将其另存为add1a.vwf文件。采用执行【Edit/Insert/Insert Nodeor Bus】菜单命令，得到下图 点击红框部分，得到下图，对下图进行点击【Flier】下拉菜单选取【Pins:all】；点击【List】按钮显示找到的节点；点击【>>...
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Determining the location of the ModelSim executable… Using: c:/intelfpga_lite/20.1/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executable
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Determining the location of the ModelSim executable... Using: c:/intelfpga_lite/18.1/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jiantongdeng1 -c jiantongdeng1 --vector_source="C:/intelFPGA_lite/18.1/Waveform.vwf" --testbench_file="C:/intelFPGA_lite/18.1/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Jul 01 16:50:48 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jiantongdeng1 -c jiantongdeng1 --vector_source=C:/intelFPGA_lite/18.1/Waveform.vwf --testbench_file=C:/intelFPGA_lite/18.1/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (199014): Vector source file C:/intelFPGA_lite/18.1/Waveform.vwf specified with --testbench_vector_input_file option does not exist Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 4612 megabytes Error: Processing ended: Tue Jul 01 16:50:49 2025 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error.
最新发布
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在解决 ModelSim 与 Quartus 联合仿真过程中出现的 `Error (199014): Vector source file ... does not exist` 错误时，需要从多个方面排查问题根源。该错误通常表明仿真工具无法找到指定的测试平台文件（如 `...
Using: C:\intelFPGA\20.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off alu -c alu --vector_source="C:/Users/18145/Downloads/alu181/alu181/alu1/Waveform2.vwf" --testbench_file="C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/Waveform2.vwf.vht" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue May 20 11:58:19 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off alu -c alu --vector_source=C:/Users/18145/Downloads/alu181/alu181/alu1/Waveform2.vwf --testbench_file=C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/Waveform2.vwf.vht Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/" alu -c alu Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue May 20 11:58:21 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/ alu -c alu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file alu.vho in folder "C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4641 megabytes Info: Processing ended: Tue May 20 11:58:22 2025 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/alu.do generated. Completed successfully. **** Running the ModelSim simulation **** C:/intelFPGA/20.1/modelsim_ase/win32aloem/vsim -c -do alu.do ** Error: vsim: CreateProcess error: 2 Error.
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当在使用 ModelSim 和 Quartus 进行联合仿真时，出现 `CreateProcess error: 2` 的错误通常表明系统无法找到指定的可执行文件或其依赖项。以下是可能的原因及其对应的解决方法： #### 可能原因及解决措施 1. **...
Determining the location of the ModelSim executable... Using: E:\intelFPGA\18.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source="E:/intelFPGA/WORK/Waveform.vwf" --testbench_file="E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:13 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source=E:/intelFPGA/WORK/Waveform.vwf --testbench_file=E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="E:/intelFPGA/WORK/simulation/qsim/" 1 -c 1 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:14 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=E:/intelFPGA/WORK/simulation/qsim/ 1 -c 1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file 1.vo in folder "E:/intelFPGA/WORK/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4725 megabytes Info: Processing ended: Thu May 22 00:35:15 2025 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** E:/intelFPGA/WORK/simulation/qsim/1.do generated. Completed successfully. **** Running the ModelSim simulation **** E:/intelFPGA/18.1/modelsim_ase/win32aloem/vsim -c -do 1.do Reading E:/intelFPGA/18.1/modelsim_ase/tcl/vsim/pref.tcl # 10.5b # do 1.do # ** Warning: (vlib-34) Library already exists at "work". # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # vsim -novopt -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.1_vlg_vec_tst # Start time: 00:35:15 on May 22,2025 # ** Error: (vsim-3170) Could not find 'work.1_vlg_vec_tst'. # Searched libraries: # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclonev # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_mf # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/220model # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/sgate # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_lnsim # E:/intelFPGA/WORK/simulation/qsim/work # Error loading design Error loading design # End time: 00:35:16 on May 22,2025, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 Error.
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