The Making of God of War III

本文回顾了《战神3》的开发过程和技术特点,包括角色模型细节、动画制作方式、光影效果实现等。特别介绍了动画师的手工制作、底层优化实践、HDR技术的应用以及对阴影效果的深入研究。

http://www.eurogamer.net/articles/the-making-of-god-of-war-iii?page=1

相当棒的一个技术回顾。


做事方式:

有些东西是建立在其强大的团队素质基础上,比如

  • 其中动画师做出来的动画比motion capture要好得多。。。
  • 底层优化,缩小代码size等东西也在不停的做

还有是出色的做事方式,持久的耐心,对品质的狂热追求----其实是艺术家的做事方式:

  • 一个哥们在shadow上钻研了3年----而且公司给他空间去做这个
  • 用来review的盘已经发出去的时候(也就是马上就压盘开卖了),一个孜孜不倦的哥们还在不停的优化,结果让最终产品的效率又提高了%8


Features:

 

奎爷在gow2里面大约5000面,gow3里面20000面。

动画由动画师手工制作,很多动作存在动画师的想象中然后实现出来,这些不是motion capture能搞定的。

动态的simulation被大量应用,头发,尾巴等,这个是由他们的techinical artist写的代码(WTF?)

 


 

camera&level的东西针对性过强,略过。

 


 

gow2在ps2上面的代码size是1.2M,非常精炼。

从这里我们可以关注下顶级工作室是怎么做事情的,毫不犹豫的底层优化,精练的代码size。。。

 

这里提到用来做hdr的技术,(hdr用16位定点或者浮点就太没诚意了,就是要用8位搞定)

  • loguv----uncharted, heavenly sword
  • rgbm----uncharted2, gow3----rgbm这么看来优于loguv

几个图片看下rgbm达到的效果:

 

 

 

 


 

motion blur有效的增加了电影感。

 


 

mlaa----从作者本人论文来看,效果和8xmsaa不相上下。

这个siggraph10有专门论文,后面单独写吧。

 

 


 

multiple&dynamic lighting

gow3没有用deferred lighting,是用spu做的多光源计算,不过这个对于ps3以外平台没有意义,其他平台的光源还是老老实实的deferred lighting就好。

而且光照很多是带shadow的。

deferred lighting可以说是局部光照(对比全局光照)进化的最终形态,带来的效果也是很赞的:

这里值得注意的一点是,gow3 team中有个哥们专门研究shadow,研究了3年。

相信他中间肯定做了其他事情,但是这个投入可见一斑。

 

 

 

 

 

下载前可以先看下教程 https://pan.quark.cn/s/16a53f4bd595 小天才电话手表刷机教程 — 基础篇 我们将为您简单的介绍小天才电话手表新机型的简单刷机以及玩法,如adb工具的使用,magisk的刷入等等。 我们会确保您看完此教程后能够对Android系统有一个最基本的认识,以及能够成功通过magisk root您的手表,并安装您需要的第三方软件。 ADB Android Debug Bridge,简称,在android developer的adb文档中是这么描述它的: 是一种多功能命令行工具,可让您与设备进行通信。 该命令有助于各种设备操作,例如安装和调试应用程序。 提供对 Unix shell 的访问,您可以使用它在设备上运行各种命令。 它是一个客户端-服务器程序。 这听起来有些难以理解,因为您也没有必要去理解它,如果您对本文中的任何关键名词产生疑惑或兴趣,您都可以在搜索引擎中去搜索它,当然,我们会对其进行简单的解释:是一款在命令行中运行的,用于对Android设备进行调试的工具,并拥有比一般用户以及程序更高的权限,所以,我们可以使用它对Android设备进行最基本的调试操作。 而在小天才电话手表上启用它,您只需要这么做: - 打开拨号盘; - 输入; - 点按打开adb调试选项。 其次是电脑上的Android SDK Platform-Tools的安装,此工具是 Android SDK 的组件。 它包括与 Android 平台交互的工具,主要由和构成,如果您接触过Android开发,必然会使用到它,因为它包含在Android Studio等IDE中,当然,您可以独立下载,在下方选择对应的版本即可: - Download SDK Platform...
### Assertions in SystemVerilog for Verification SystemVerilog assertions (SVAs) play a crucial role in the verification of digital designs. They are used to specify design behavior and check that the design under test (DUT) adheres to its specification. SVAs can be embedded directly into the RTL code or used within testbenches to monitor and check the behavior of the design during simulation. Assertions are divided into two main categories: immediate and concurrent. Immediate assertions are used to check properties that are evaluated immediately when the assertion is executed. They are typically used in procedural blocks and are useful for checking conditions that should hold true at specific points in the simulation. Concurrent assertions, on the other hand, are used to check properties that span multiple clock cycles. They are based on temporal logic and are used to verify the sequence of events over time. The use of assertions in SystemVerilog provides several benefits. One of the primary advantages is that they help in early bug detection. By placing assertions throughout the design, it is possible to catch errors closer to the source, which can significantly reduce the time required to debug and fix issues. Additionally, assertions serve as a form of documentation, making the design intent more explicit and aiding in the understanding of complex behaviors. Best practices for using assertions in SystemVerilog include: - **Coverage-Driven Verification**: Assertions should be part of a coverage-driven verification strategy where both functional coverage and assertion coverage are considered. Functional coverage measures how well the design's functionality has been exercised, while assertion coverage indicates how often each assertion has been evaluated during simulation. - **Modular and Reusable Code**: Design assertions to be modular and reusable. This can be achieved by encapsulating common sequences and properties into reusable components, which can then be easily integrated into different parts of the design or across different projects. - **Effective Use of Coverage**: Utilize coverage metrics to ensure that assertions are being triggered and evaluated as expected. This helps in identifying untested parts of the design and ensures that the testbench is exercising all relevant scenarios. - **Debugging and Logging**: Implement mechanisms for debugging and logging assertion failures. When an assertion fails, having detailed logs can help in quickly identifying the cause of the failure and the context in which it occurred. - **Performance Considerations**: Be mindful of the performance impact that assertions may have on simulation speed. While it is important to have thorough assertion coverage, excessive use of assertions can lead to longer simulation times. Therefore, it is essential to strike a balance between the number of assertions and the simulation performance. By following these best practices, engineers can leverage SystemVerilog assertions to enhance the quality and reliability of their designs, ensuring that the final product meets the desired specifications and performs reliably under various operating conditions. ```systemverilog // Example of a simple immediate assertion initial begin int a = 5; assert (a == 5) else $error("Assertion failed: a is not equal to 5"); end // Example of a concurrent assertion property p_example; @(posedge clk) disable iff (reset) a ##1 b ##1 c; endproperty assert property (p_example) else $error("Concurrent assertion failed"); ``` ###
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值