Understanding the linux kernel-ch6-Timing Measurements

6.1 Clock and Timer Circuits
	Real Time Clock (RTC)
		Motorola 146818
		IRQ 8
		2 Hz and 8,192 Hz
		The kernel accesses the RTC through the 0x70 and 0x71 I/O ports
		Linux uses the RTC only to derive the time and date; however,
		it allows processes to program the RTC by acting on the /dev/rtc device file
	Time Stamp Counter (TSC)
		Time Stamp Counter(TSC) register
		rdtsc assembly language instruction
		calibrate_tsc( ) function computes the frequency by counting the number of clock signals
		that occur in a time interval of approximately 5 milliseconds
	Programmable Interval Timer (PIT)
		usually implemented by an 8254 CMOS chip using the 0x40-0x43 I/O ports
		IRQ 0 at a (roughly) 1000-Hz frequency that is, once every 1 millisecond
		· HZ		# define HZ		1000		/* Internal kernel timer frequency */
		· CLOCK_TICK_RATE		#  define CLOCK_TICK_RATE 1193182 /* Underlying HZ */
		· LATCH		#define LATCH  ((CLOCK_TICK_RATE + HZ/2) / HZ)	/* For divider */
		void setup_pit_timer(void)
		{
			extern spinlock_t i8253_lock;
			unsigned long flags;
			spin_lock_irqsave(&i8253_lock, flags);
			outb_p(0x34,PIT_MODE);		/* binary, mode 2, LSB/MSB, ch 0 */
			udelay(10);
			outb_p(LATCH & 0xff , PIT_CH0);	/* LSB */
			udelay(10);
			outb(LATCH >> 8 , PIT_CH0);	/* MSB */
			spin_unlock_irqrestore(&i8253_lock, flags);
		}
	CPU Local Timer
		The CPU local timer is a device similar to the Programmable Interval Timer
		just described that can issue one-shot or periodic interrupts.
		There are, however, a few differences:
		· The APIC's timer counter is 32 bits long, while the PIT's timer counter is 16 bits long;
		therefore, the local timer can be programmed to issue interrupts at very low frequencies
		· The local APIC timer sends an interrupt only to its processor, while the
		PIT raises a global interrupt, which may be handled by any CPU in the system.
		· The APIC's timer is based on the bus clock signal (or the APIC bus signal,
		in older machines). It can be programmed in such a way to decrease
		the timer counter every 1, 2, 4, 8, 16, 32, 64, or 128 bus clock signals
		Conversely, the PIT, which makes use of its own clock signals,
		can be programmed in a more flexible way
	High Precision Event Timer (HPET)
		· chip includes up to eight 32-bit or 64-bit independent counters .
		Each counter is driven by its own clock signal, whose frequency must be at least 10 MHz;
		· Any counter is associated with at most 32 timers, each of
		which is composed by a comparator and a match register.
		The comparator is a circuit that checks the value in the counter
		gainst the value in the match register, and raises a hardware interrupt if a match is found.
		· The HPET chip can be programmed through registers mapped into memory space
		The BIOS establishes the mapping during the bootstrapping phase
		and reports to the operating system kernel its initial memory address
	ACPI Power Management Timer
		· The ACPI Power Management Timer (or ACPI PMT) is yet another clock device
		included in almost all ACPI-based motherboards
		Its clock signal has a fixed frequency of roughly 3.58 MHz
		· The ACPI Power Management Timer is preferable to the TSC
		if the operating system or the BIOS may dynamically
		lower the frequency or voltage of the CPU to save battery power.
		· if an HPET device is present, it should always
		be preferred to the other circuits because of its richer architecture