Understanding the linux kernel-ch2-Memory addressing

Chapter 2. Memory Addressing

2.1. Memory Addresses

Logical address:consist of a 16-bit Segment Selector and a 32-bit Offset

Linear address (also known as virtual address)

Physical address

arbiter

Memory Management Unit (MMU)

segmentation unit

transforms a logical address into a linear address

1,Examines the TI field of the Segment Selector to determine which Descriptor Table stores the Segment Descriptor.

2,Computes the address of the Segment Descriptor from the index field of the Segment Selector

3,Adds the offset of the logical address to the Base field of the Segment Descriptor, thus obtaining the linear address

paging unit

transforms the linear address into a physical address

2.2. Segmentation in Hardware

real mode

protected mode

Segment Selectors

bit15

bit2

bit1

bit0

index

TI

RPL

segmentation registers(cs, ss, ds, es, fs, gs)

cs register : includes a 2-bit field that specifies the Current Privilege Level (CPL) of the CPU.

The value 0 denotes the highest privilege level, while the value 3 denotes the lowest one.

Linux uses only levels 0 and 3, which are respectively called Kernel Mode and User Mode.

Segment Descriptors

Segment Descriptors(8-byte) are stored either in the Global Descriptor Table (GDT ) or in the Local Descriptor Table(LDT).

gdtr control register.

ldtr control register.

a Task State Segment (TSS):save the contents of the processor

Local Descriptor Table Descriptor (LDTD)

Data segment descripter

bit63

bit55

bit54

bit53

bit52

bit51

BASE(24-31)

G

B

0

AVL

LIMIT(16-19)

bit47

bit46

bit44

bit43

bit39

bit15

bit0

1

DPL

S==1

TYPE

BASE(0-23)

LIMIT(0-15)

Code segment descripter

bit63

bit55

bit54

bit53

bit52

bit51

BASE(24-31)

G

D

0

AVL

LIMIT(16-19)

bit47

bit46

bit44

bit43

bit39

bit15

bit0

1

DPL

S==1

TYPE

BASE(0-23)

LIMIT(0-15)

System segment descripter

bit63

bit55

bit54

bit53

bit52

bit51

BASE(24-31)

G

0

LIMIT(16-19)

bit47

bit46

bit44

bit43

bit39

bit15

bit0

1

DPL

S==1

TYPE

BASE(0-23)

LIMIT(0-15)

2.3. Segmentation in Linux

Linux prefers paging to segmentation for the following reasons:

Memory management is simpler when all processes use the same segment register values that is,

when they share the same set of linear addresses

One of the design objectives of Linux is portability to a wide range of architectures;

RISC architectures in particular have limited support for segmentation.

_ _USER_CS, _ _USER_DS, _ _KERNEL_CS, and _ _KERNEL_DS

The Linux GDT

The Linux LDTs

2.4. Paging in Hardware

PG flag of cr0

Page Directory

Page Table

The physical address of the Page Directory in use is stored in a control register named cr3

The Directory field within the linear address determines the entry in the Page Directory that points to the proper Page Table.

The address's Table field, in turn, determines the entry in the Page Table that

contains the physical address of the page frame containing the page.

The Offset field determines the relative position within the page frame

Linear address

bot31

bit21

bit11

bit0

Directory

Table

Offset

The entries of Page Directories and Page Tables have the same structure. Each entry includes the following fields:

Present flag

Field containing the 20 most significant bits of a page frame physical address

Accessed flag

Dirty flag

Read/Write flag

0: the corresponding Page Table or page can only be read; 1: can be read and written

User/Supervisor flag

0: the page can be addressed only when the CPL is less than 3 (this means, Kernel Mode).

PCD and PWT flags

1: the page can always be addressed

Page Size flag

Global flag

extended paging

PSE flag of the cr4

Linear address

bot31

bit21

bit0

Directory

Offset

Physical Address Extension (PAE)

the number of address pins on its processors from 32 to 36

all Intel processors are now able to address up to 236 = 64 GB

PAE is activated by setting the Physical Address Extension (PAE) flag in the cr4 control register

32 bit liner address to 36 bit physical address

When mapping linear addresses to 4 KB pages

cr3

Points to a PDPT

bits 31-30

Point to 1 of 4 possible entries in PDPT

bits 29-21

Point to 1 of 512 possible entries in Page Directory

bits 20-12

Point to 1 of 512 possible entries in Page Table

bits 11-1

Offset of 4-KB page

When mapping linear addresses to 2-MB pages (PS flag set in Page Directory entry),

the 32 bits of a linear address are interpreted in the following way:

cr3

Points to a PDPT

bits 31-30

Point to 1 of 4 possible entries in PDPT

bits 29-21

Point to 1 of 512 possible entries in Page Directory

bits 20-0

Offset of 2-MB page

hardware cache

write-through

write-back

CD flag of the cr0 processor register is used to enable or disable the cache circuitry

The NW flag specifies whether the write-through or the write-back strategy is used for the caches

each Page Directory and each Page Table entry includes two flags: PCD (Page Cache Disable)

PWT (Page Write-Through), which specifies whether the write-back or the write-through

strategy must be applied while writing data into the page frame

caching is enabled for all page frames, and the write-back strategy is always adopted for writing for linux.

Translation Lookaside Buffers (TLB)

speed up linear address translation. When a linear address is used for the first time,

the corresponding physical address is computed through slow accesses to the Page Tables in RAM.

The physical address is then stored in a TLB entry so that further references

to the same linear address can be quickly translated.

2.5. Paging in Linux

a four-level paging model

Page Global Directory

Page Upper Directory

Page Middle Directory

Page Table

The Linear Address Fields

Macros OP The Linear Address Fields

#define PAGE_SHIFT 12

#define PAGE_SIZE  ((UL)1 << PAGE_SHIFT)

#define PAGE_MASK (~(PAGE_SIZE  -1))

#ifdef PAE

#define PMD_SHIFT 21

#else

#define PMD_SHIFT 22

#define PMD_SIZE ((UL)1 << PMD_SHIFT)

#defnie PMD_MASK  (~(PMD_SIZE -1))

PUD_SHIFT

PUD_SIZE

PUD_MASK

PGDIR_SHIFT

PGDIR_SIZE

PGDIR_MASK

PTRS_PER_PTE, PTRS_PER_PMD, PTRS_PER_PUD, PTRS_PER_PGD

Page Table Handling

_ _ pte, _ _ pmd, _ _ pud, _ _ pgd, _ _ pgprot

pte_val, pmd_val, pud_val, pgd_val, pgprot_val

pte_none, pmd_none, pud_none, pgd_none

pte_clear, pmd_clear, pud_clear, pgd_clear

set_pte, set_pmd, set_pud, set_pgd

pte_same(a,b)

pmd_large(e)

pmd_bad

Page flag reading functions

Page flag setting functions

Macros acting on Page Table entries

Page allocation functions

Physical Memory Layout

Example of BIOS-provided physical addresses map

Process Page Tables

The linear address space of a process is divided into two parts:

from 0x00000000 to 0xbfffffff can be addressed when the process runs in either User or Kernel Mode.

from 0xc0000000 to 0xffffffff can be addressed only when the process runs in Kernel Mode

PAGE_OFFSET 0xc0000000

Kernel Page Tables

Provisional kernel Page Tables

Final kernel Page Table

Fix-Mapped Linear Addresses

Handling the Hardware Cache and the TLB