module Eth_SM_Packet_TOP#(
parameter NUM_SM_IF = 1,
parameter NUM_FH = 18
)
(
// Clock rst
input wire i_156p25m_clk [NUM_SM_IF-1:0] , // 156.25M for SM_IF 10G
input wire i_156p25m_rst [NUM_SM_IF-1:0] ,
input wire i_pbus_clk , // for pbus
input wire i_pbus_rst , // for pbus
input wire i_CPU_WEB ,
input wire i_CPU_REB ,
input wire [11:0] i_CPU_ADDR ,
input wire [07:0] i_CPU_WDATA ,
output wire [07:0] o_CPU_RDATA ,
// AXI4_Stream Ports: DATA Egress(DL) GEN I/O
output logic [63:00] o_SM_IF_DL_gen_axis_tdata [NUM_SM_IF-1:0],
output logic [07:00] o_SM_IF_DL_gen_axis_tkeep [NUM_SM_IF-1:0],
output logic o_SM_IF_DL_gen_axis_tlast [NUM_SM_IF-1:0],
input logic i_SM_IF_DL_gen_axis_tready [NUM_SM_IF-1:0],
output logic o_SM_IF_DL_gen_axis_tvalid [NUM_SM_IF-1:0]
);
wire i_frame_tick ='b0;
wire[00:00] w_156m_rst [NUM_SM_IF-1:0];
wire[00:00] w_156m_rst_n [NUM_SM_IF-1:0];
wire w_pbus_rst ;
wire[NUM_SM_IF-1:00] w_reset_sm_dl_pkg_gen ; // : out std_logic_vector (NUM_SM_IF-1 downto 0) ;
wire[NUM_SM_IF-1:00] w_refresh_sm_dl_pkg_gen ; // : out std_logic_vector (NUM_SM_IF-1 downto 0) ;
// -- GEN TICK
wire[NUM_SM_IF-1:00] w_sm_dl_pkg_gen_tick ; // : out std_logic_vector (NUM_SM_IF-1 downto 0) ;
wire[48-1:00] w_sm_dl_da [NUM_SM_IF-1:00]; // : out std_logic_array48 (NUM_SM_IF-1 downto 0) ; -- F00:805
wire[48-1:00] w_sm_dl_sa [NUM_SM_IF-1:00]; // : out std_logic_array48 (NUM_SM_IF-1 downto 0) ; -- F08:80C
wire[16-1:00] w_sm_dl_pkt_payload_lens [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F10:811
wire[ 8-1:00] w_sm_dl_vlan_en [NUM_SM_IF-1:00]; // : out std_logic_array8 (NUM_SM_IF-1 downto 0) ; -- F12
wire[16-1:00] w_sm_dl_ether_type_0 [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
wire[16-1:00] w_sm_dl_ether_type_1 [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
wire[16-1:00] w_sm_dl_ether_type_2 [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
wire[16-1:00] w_message_resp [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
wire[16-1:00] w_message_sync [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
wire[16-1:00] w_sm_dl_vlan_id_field_0 [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F16:817
wire[16-1:00] w_sm_dl_vlan_id_field_1 [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F16:817
wire[16-1:00] w_sm_dl_vlan_id_field_2 [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F16:817
wire[ 8-1:00] w_sm_dl_packet_type [NUM_SM_IF-1:00]; // : out std_logic_array8 (NUM_SM_IF-1 downto 0) ; -- F18
//wire[64-1:00] w_sm_dl_data_id [NUM_SM_IF-1:00]; // : out std_logic_array48 (NUM_SM_IF-1 downto 0) ; -- F20:827
wire[16-1:00] w_sm_dl_gen_times [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- 829:82A
wire[16-1:00] w_sm_dl_gen_gaps [NUM_SM_IF-1:00]; // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- 82B:82C
wire[NUM_FH-1 :00] w_reset_sm_dl_chk ; // : out std_logic_vector (NUM_FH-1 downto 0) ;
wire[8 -1 :00] w_bk_2_bk ; // : out std_logic_vector (NUM_FH-1 downto 0) ;
v_rst_sync #( .DLY_NUM ( 2), .MAX_FANOUT_NUM (100) ) uR0_rst_cpu_if
(
.i_rst_in (i_pbus_rst ),
.i_clk (i_pbus_clk ),
.o_rst_out (w_pbus_rst )
);
genvar n;
for (n=0;n<NUM_SM_IF;n=n+1) begin
// uRx: reset
v_rst_sync #( .DLY_NUM ( 2), .MAX_FANOUT_NUM (100) ) uR1_rst_156m_sm_gen
(
.i_rst_in (i_156p25m_rst[n] ),
.i_clk (i_156p25m_clk[n] ),
.o_rst_out (w_156m_rst[n] )
);
end
// U00: CPU_IF
Eth_SM_Packet_cpu_if#(
.NUM_SM_IF (NUM_SM_IF),
.NUM_FH (NUM_FH )
)
U00_Eth_SM_Packet_cpu_if(
// -------- Reset
.CPU_RST ( w_pbus_rst ), // : in std_logic ; -- RST_100M
// -------- CLK
.CPU_CLK ( i_pbus_clk ), // : in std_logic ; -- CLK_100M
// -------- CPU IF----------
.CPU_WEB (i_CPU_WEB ), // : in std_logic;
.CPU_REB (i_CPU_REB ), // : in std_logic;
.CPU_ADDR (i_CPU_ADDR ), // : in std_logic_vector(11 downto 0);
.CPU_WDATA (i_CPU_WDATA ), // : in std_logic_vector(7 downto 0) ;
.CPU_RDATA (o_CPU_RDATA ), // : out std_logic_vector(7 downto 0) ;
// -- RESET & Para refresh
// -- PKT_GEN DL for 10G SM IF side 0xCFF0:0xCFF7
.O_RESET_SM_DL_PKG_GEN (w_reset_sm_dl_pkg_gen ), // : out std_logic_vector (NUM_SM_IF-1 downto 0) ;
.O_Refresh_SM_DL_PKG_GEN (w_refresh_sm_dl_pkg_gen ), // : out std_logic_vector (NUM_SM_IF-1 downto 0) ;
// -- PKT_GEN UL for 25G FH side 0xCFF8:0xCFFF
.O_RESET_SM_UL_PKG_GEN ( ), //(w_reset_sm_ul_pkg_gen ), // : out std_logic_vector (NUM_FH-1 downto 0) ;
.O_Refresh_SM_UL_PKG_GEN ( ), //(w_refresh_sm_ul_pkg_gen), // : out std_logic_vector (NUM_FH-1 downto 0) ;
.O_SM_DL_PKG_GEN_TICK (w_sm_dl_pkg_gen_tick ), // : out std_logic_vector (NUM_SM_IF-1 downto 0) ;
// -- GEN TICK UL 0xCF07:0xCF07
.O_SM_UL_PKG_GEN_TICK ( ), //(w_sm_ul_pkg_gen_tick ), // : out std_logic_vector (NUM_FH-1 downto 0) ;
// -- PKT_GEN DL for 10G SM IF side 0xCF00:0xCF3F
.O_SM_DL_DA (w_sm_dl_da ), // : out std_logic_array48 (NUM_SM_IF-1 downto 0) ; -- F00:805
.O_SM_DL_SA (w_sm_dl_sa ), // : out std_logic_array48 (NUM_SM_IF-1 downto 0) ; -- F08:80C
.O_SM_DL_pkt_payload_lens (w_sm_dl_pkt_payload_lens ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F10:811
.O_SM_DL_VLAN_en (w_sm_dl_vlan_en ), // : out std_logic_array8 (NUM_SM_IF-1 downto 0) ; -- F12
.O_SM_DL_ether_type_0 (w_sm_dl_ether_type_0 ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
.O_SM_DL_ether_type_1 (w_sm_dl_ether_type_1 ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
.O_SM_DL_ether_type_2 (w_sm_dl_ether_type_2 ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
.O_SM_DL_message_sync (w_message_sync ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
.O_SM_DL_message_resp (w_message_resp ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F14:815
.O_SM_DL_VLAN_ID_Field_0 (w_sm_dl_vlan_id_field_0 ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F16:817
.O_SM_DL_VLAN_ID_Field_1 (w_sm_dl_vlan_id_field_1 ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F16:817
.O_SM_DL_VLAN_ID_Field_2 (w_sm_dl_vlan_id_field_2 ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- F16:817
.O_SM_DL_packet_type (w_sm_dl_packet_type ), // : out std_logic_array8 (NUM_SM_IF-1 downto 0) ; -- F18
.O_SM_DL_data_id ( ), //(w_sm_dl_data_id ), // : out std_logic_array48 (NUM_SM_IF-1 downto 0) ; -- F20:827
.O_SM_DL_GEN_TIMES (w_sm_dl_gen_times ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- 829:82A
.O_SM_DL_GEN_GAPS (w_sm_dl_gen_gaps ), // : out std_logic_array16 (NUM_SM_IF-1 downto 0) ; -- 82B:82C
.O_BK_2_BK (w_bk_2_bk ),
// -- PKT_GEN UL for 25G FH side 0xC800:0xCC7F
.O_SM_UL_DA ( ), //(w_sm_ul_da ), // : out std_logic_array48 (NUM_FH-1 downto 0) ; -- F00:805
.O_SM_UL_SA ( ), //(w_sm_ul_sa ), // : out std_logic_array48 (NUM_FH-1 downto 0) ; -- F08:80C
.O_SM_UL_pkt_payload_lens ( ), //(w_sm_ul_pkt_payload_lens ), // : out std_logic_array16 (NUM_FH-1 downto 0) ; -- F10:811
.O_SM_UL_VLAN_en ( ), //(w_sm_ul_vlan_en ), // : out std_logic_array8 (NUM_FH-1 downto 0) ; -- F12
.O_SM_UL_ether_type ( ), //(w_sm_dl_ether_type ), // : out std_logic_array16 (NUM_FH-1 downto 0) ; -- F14:815
.O_SM_UL_VLAN_ID_Field ( ), //(w_sm_ul_vlan_id_field ), // : out std_logic_array16 (NUM_FH-1 downto 0) ; -- F16:817
.O_SM_UL_packet_type ( ), //(w_sm_ul_packet_type ), // : out std_logic_array8 (NUM_FH-1 downto 0) ; -- F18
.O_SM_UL_data_id ( ), //(w_sm_ul_data_id ), // : out std_logic_array48 (NUM_FH-1 downto 0) ; -- F20:827
.O_SM_UL_GEN_TIMES ( ), //(w_sm_ul_gen_times ), // : out std_logic_array16 (NUM_FH-1 downto 0) ; -- 829:82A
.O_SM_UL_GEN_GAPS ( ) //(w_sm_ul_gen_gaps ) // : out std_logic_array16 (NUM_FH-1 downto 0) -- 82B:82C
);
Eth_SM_Packet_GEN U1_Eth_SM_Packet_GEN_DL
(
.i_clk (i_156p25m_clk[0] ), // 156.25M for SM_IF or 390M for PTP/XBAR
.i_rst (w_156m_rst[0]|w_reset_sm_dl_pkg_gen[0]),
// Configuration Ports
.i_packet_type (w_sm_dl_packet_type[0] ), //s package : [07:07]==1;m package : [07:07]==0;[03:00] Packet Type
.i_DA_ADDR (w_sm_dl_da[0] ),
.i_SA_ADDR (w_sm_dl_sa[0] ),
.i_payload_length (w_sm_dl_pkt_payload_lens[0] ), // payload length : 16K Maxmium
.i_ether_type_0 (w_sm_dl_ether_type_0[0] ),
.i_ether_type_1 (w_sm_dl_ether_type_1[0] ),
.i_ether_type_2 (w_sm_dl_ether_type_2[0] ),
.i_message_resp (w_message_resp[0] ),
.i_message_sync (w_message_sync[0] ),
.i_VLAN_en (w_sm_dl_vlan_en[0] ),
.i_bk_2_bk (w_bk_2_bk ),
// VLAN TAG: TPID[31:16]+VLAN_PCP[15:13]+VLAN_DEI[12:12]+VLAN_VID[11:00]
.i_VLAN_Field_0 (w_sm_dl_vlan_id_field_0[0] ), // Used as VLAN identifiers GUC1: FH00-FH17(0x000-0x012)
.i_VLAN_Field_1 (w_sm_dl_vlan_id_field_1[0] ), // Used as VLAN identifiers GUC1: FH00-FH17(0x000-0x012)
.i_VLAN_Field_2 (w_sm_dl_vlan_id_field_2[0] ), // Used as VLAN identifiers GUC1: FH00-FH17(0x000-0x012)
.i_force_para_refresh (w_refresh_sm_dl_pkg_gen[0] ), // Force refresh GEN para
.i_gen_times (w_sm_dl_gen_times[0] ), // 0:always no gap
.i_gen_gap (w_sm_dl_gen_gaps[0] ), // clock
.i_gen_tick (w_sm_dl_pkg_gen_tick[0] ), // TICK for PKT GEN: next clock will gen the MS Packets
.i_frame_tick (w_refresh_sm_dl_pkg_gen ),
.o_axis_eth_tdata (o_SM_IF_DL_gen_axis_tdata[0] ),
.o_axis_eth_tkeep (o_SM_IF_DL_gen_axis_tkeep[0] ),
.o_axis_eth_tlast (o_SM_IF_DL_gen_axis_tlast[0] ),
.i_axis_eth_tready (i_SM_IF_DL_gen_axis_tready[0] ),
.o_axis_eth_tvalid (o_SM_IF_DL_gen_axis_tvalid[0] )
);
endmodule 你是5G通信的专家，请给我分析这段代码、接口，总体是在实现什么功能，例化的模块分别什么作用
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本文详细介绍了电力载波通信数据帧结构及其与RS485数据帧的兼容性。通过对比两者帧格式，阐述了载波通信在数据传输过程中的容错性和安全性增强机制。
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