SPI-Interface

最新推荐文章于 2025-02-09 20:34:36 发布

原创最新推荐文章于 2025-02-09 20:34:36 发布 · 453 阅读

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本文详细介绍了SPI总线的四个逻辑信号：串行时钟(SCLK)、主出从入(MOSI)、主入从出(MISO)及从机选择(SS)的功能与连接方式，并解释了不同设备上的信号名称差异及两种片选信号控制模式。

The SPI bus specifies four logic signals:

SCLK: Serial Clock (output from master)
MOSI: Master Out Slave In (data output from master)
MISO: Master In Slave Out (data output from slave)
SS: Slave Select (often active low, output from master)

MOSI on a master connects to MOSI on a slave. MISO on a master connects to MISO on a slave. Slave Select has the same functionality as chip select and is used instead of an addressing concept.

Note: on a slave-only device, MOSI may be labeled as SDI (Slave Data In) and MISO may be labeled as SDO (Slave Data Out)

The signal names above can be used to label both the master and slave device pins as well as the signal lines between them in an unambiguous way, and are the most common in modern products. Pin names are always capitalized e.g. "Slave Select," not "slave select."

Older products can have nonstandard SPI pin names:

Serial Clock:

Master Output → Slave Input (MOSI):

SIMO, MTSR - correspond to MOSI on both master and slave devices, connects to each other
SDI, DI, DIN, SI - on slave devices; connects to MOSI on master, or to below connections
SDO, DO, DOUT, SO - on master devices; connects to MOSI on slave, or to above connections

Master Input ← Slave Output (MISO):

SOMI, MRST - correspond to MISO on both master and slave devices, connects to each other
SDO, DO, DOUT, SO - on slave devices; connects to MISO on master, or to below connections
SDI, DI, DIN, SI - on master devices; connects to MISO on slave, or to above connections

Slave Select:

SS, SS, SSEL, nSS, /SS, SS# (slave select)
CS, CS (chip select)
CSN (chip select/enable)
CE (chip enable)

1,硬件NSS,是指SPI自动控制SPI的片选信号,发送数据的时候,输出低电平,不发送的时候,是高电平,这个模式一般不用.因为这种方式只能1个SPI接1个从机,很是蛋疼.
2,软件模式就是完全软件控制SPI片选,就是一个普通IO控制,你要SPI通信之前,必须先用软件的方式,控制SPI从机的片选为低电平,然后在发送数据.发完后,拉高. 一般用这个模式,因为可以一个SPI控制N多个从机...