2K Page NAND ECC说明

本文介绍了一种针对NAND Flash存储设备的页面读写操作方法,并详细阐述了ECC(错误检查与纠正)校验码的生成与验证过程。通过具体的C语言代码实现,展示了如何进行NAND Flash的页面写入与读取,以及如何确保数据的完整性和可靠性。

2K Page K9K8G08 WritePage ReadPage  

static U32 WritePage(U32 addr, U8 *buf)

{
 U32 i, mecc, secc;
 U8 stat, tmp[6], value;
 
 addr &= ~0x3f;
 
 InitEcc();   //复位ECC
 MEccUnlock();   //解锁Main区ECC
 NFChipEn();   //打开nandflash片选
 WaitNFBusy();   //等待忙信号
 WrNFCmd(0x80);  //页写命令周期1
 
 WrNFAddr(0x00);  //列地址A0~A7
 WrNFAddr(0x00);  //列地址A8~A11
 WrNFAddr((addr>>0)& 0xFF); //行地址A12~A19
 WrNFAddr((addr>>8)& 0xFF); //行地址A20~A27
 WrNFAddr((addr>>16)& 0xFF); //行地址A28~A30
  
 for(i=0; i<2048; i++)
  WrNFDat(buf[i]); //写一页数据
 
 WaitNFBusy();   //等待忙信号
 MEccLock();   //锁定Main区的ECC校验码
 mecc = RdNFMEcc();  //读取Main区的ECC校验码

 //把Main区的ECC校验码由字型转换成字节型并保存到零时数组里
 tmp[0] = (U8)(mecc&0xff);  
 tmp[1] = (U8)((mecc>>8)&0xff);
 tmp[2] = (U8)((mecc>>16)&0xff);
 tmp[3] = (U8)((mecc>>24)&0xff);
    
 SEccUnlock();   //解锁Spare区的ECC
 
 //把Main区的ECC值写入到Spare区的前四个字节,即第2048~2051地址
 WrNFDat(tmp[0]);
 WrNFDat(tmp[1]);
 WrNFDat(tmp[2]);
 WrNFDat(tmp[3]);
 
 SEccLock();   //锁定Spare区的ECC校验码
 secc = RdNFSEcc();  //读取Spare区的ECC校验码
 
 //把Spare区的ECC校验码由字型转换成字节型并保存到零时数组里
 tmp[4] = (U8)(secc&0xff);
 tmp[5] = (U8)((secc>>8)&0xff);
 
 //把Spare区的ECC值写入到Spare区的第2052~2053地址
 WrNFDat(tmp[4]);
 WrNFDat(tmp[5]);
 
 WrNFCmd(0x10);  //页写命令周期2
 WaitNFBusy();   //等待忙信号
 WrNFCmd(0x70);  //写读状态命令
 WaitNFBusy();   //等待忙信号
 stat = RdNFDat();  //读取状态字
 NFChipDs();   //关闭nandflash片选
 if(stat&0x01)
 {
     MarkBadBlk(addr);  //标注坏块
     puts("WritePage Error!\n"); //写操作失败
     return 0;    //写操作失败
 }
 puts("WritePage No Error!\n"); //写操作成功
 return 1;    //写操作成功  
}

 

static void ReadPage(U32 addr, U8 *buf)
{
 U32 i, mecc, secc;
 
 addr &= ~0x3f;

 InitEcc();   //复位ECC
 MEccUnlock();   //解锁Main区ECC
 NFChipEn();   //打开nandflash片选
 WaitNFBusy();   //等待忙信号 
 WrNFCmd(0x00);  //页读命令周期1

 WrNFAddr(0x00);  //列地址A0~A7
 WrNFAddr(0x00);  //列地址A8~A11
 WrNFAddr((addr>>0)& 0xFF); //行地址A12~A19
 WrNFAddr((addr>>8)& 0xFF); //行地址A20~A27
 WrNFAddr((addr>>16)& 0xFF); //行地址A28~A30
 
 WrNFCmd(0x30);  //页读命令周期2
 WaitNFBusy();   //等待忙信号
 
 for(i=0; i<2048; i++)
  buf[i] = RdNFDat(); //读取一页数据
 WaitNFBusy();   //等待忙信号

 MEccLock();   //锁定main区的ECC值

 SEccUnlock();   //解锁spare区的ECC值
 
 mecc = RdNFDat32();  //读取spare区的前4个地址内容,即2048~2051,这四个字节是main区的ECC值 
 buf[i+1] =  (U8)(mecc & 0xff);  //把读取到的main区的ECC校验码放入到零时数组里
 buf[i+2] =  (U8)((mecc>>8) & 0xff); //把读取到的main区的ECC校验码放入到零时数组里
 buf[i+3] =  (U8)((mecc>>16) & 0xff); //把读取到的main区的ECC校验码放入到零时数组里
 buf[i+4] =  (U8)((mecc>>24) & 0xff); //把读取到的main区的ECC校验码放入到零时数组里

 //把读取到的main区的ECC校验码放入到NFMECCD0/1的相应位置   
 rNFMECCD0 =  ((mecc&0xff00)<<8)|(mecc&0xff);
 rNFMECCD1 =  ((mecc&0xff000000)>>8)|((mecc&0xff0000)>>16);
 
 SEccLock();  //锁定spare区的ECC值
 
 secc = RdNFDat32(); //读取spare区的4个地址内容,即2052~2055,其中前两个字节是spare区的ECC值
 
 buf[i+5] = (U8)(secc & 0xff);   //把读取到的spare区的ECC校验码放入到零时数组里
 buf[i+6] = (U8)((secc>>8) & 0xff);   //把读取到的spare区的ECC校验码放入到零时数组里
 buf[i+7] = (U8)((secc>>16) & 0xff);  //把读取到的spare区的ECC校验码放入到零时数组里
 buf[i+8] = (U8)((secc>>24) & 0xff);  //把读取到的spare区的ECC校验码放入到零时数组里
 rNFSECCD = ((secc&0xff00)<<8)|(secc&0xff); //把读取到的spare区的ECC校验码放入到NFSECCD的相应位置   
 
 NFChipDs();    //关闭nandflash片选
 
 if(((rNFESTAT0)&0x0f)==0)  //判断main data area 和 spear date area 是否有bit位出错
  puts("ECC No Error!\n"); //有ECC错误
 else
  puts("ECC Error!\n"); //没有ECC错误
 puts("0x%8x\n",(rNFESTAT0)); //显示读到的rNFESTAT0寄存器
}

/* * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */ #include <common.h> #include <linux/mtd/rawnand.h> #include <linux/sizes.h> #ifdef CONFIG_HSAN #include <hi_nand.h> #endif #define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) #define SP_OPTIONS NAND_NEED_READRDY #define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16) /* * The chip ID list: * name, device ID, page size, chip size in MiB, eraseblock size, options * * If page size and eraseblock size are 0, the sizes are taken from the * extended chip ID. */ struct nand_flash_dev nand_flash_ids[] = { #ifdef CONFIG_MTD_NAND_MUSEUM_IDS LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS), #endif #ifdef CONFIG_HSAN {"S34ML02G1", { .id = {0x01, 0xDA, 0x90, 0x95, 0x44} }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_NAND_E }, {"S34ML02G2", { .id = {0x01, 0xF1, 0x80, 0x1D} }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 4, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_NAND_E }, {"S34ML04G2", { .id = {0x01, 0xDC, 0x90, 0x95, 0x56} }, .pagesize = SZ_2K, .chipsize = SZ_512, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_NAND_E }, {"MT29F2G08ABAGAWP-IT:G", { .id = {0x2C, 0xDA, 0x90, 0x95, 0x06} }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_NAND_E }, {"MX35LF1GE4AB", { .id = {0xC2, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, .pagesize = SZ_2K, .chipsize = SZ_128, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"MX35LF2G14AC", { .id = {0xC2, 0x20, 0xC2, 0x20, 0xC2, 0xF0, 0x9F, 0xE5} }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"MX35LF2G24AD", { .id = {0xC2, 0x24, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00} }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 3, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"GD5F2GQ4UE9IG", { .id = { 0xC8, 0xD2, 0xC8, 0xD2, 0xC8, 0xFF, 0xFF, 0xFF } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"GD5F2GM7UEYIGR", { .id = { 0xC8, 0x92, 0xC8, 0x92, 0xC8, 0xFF, 0xFF, 0xFF } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"GD5F1GQ4xExIH", { .id = { 0xC8, 0xD9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_STD_E, HI_SPI_NAND_CMD_READ, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_STD_E, HI_SPI_NAND_CMD_PP, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x0, .hi_status_feature_reg = 0x0, {0} }, {"w25n01gv", { .id = { 0xEF, 0xAA, 0x21, 0x00, 0x00, 0xFF, 0xFF, 0xFF } }, .pagesize = SZ_2K, .chipsize = SZ_128, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_STD_E, HI_SPI_NAND_CMD_READ, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_STD_E, HI_SPI_NAND_CMD_PP, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x8, .hi_status_feature_reg = 0x0, {0} }, {"WS21SFVC32GA", { .id = { 0x2C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x0, .hi_status_feature_reg = 0x0, {0} }, {"QXSND2GUIB-GT", { .id = { 0x2C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 128, NAND_ECC_INFO(16, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x0, .hi_status_feature_reg = 0x0, {0} }, {"DS35Q2GA", { .id = { 0xe5, 0x72, 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"DS35Q1GA", { .id = { 0xe5, 0x71, 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_128, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"DS35Q1GB", { .id = { 0xe5, 0xf1, 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_128, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .unique_id_if = HI_SPI_NAND_READ_UID_IF_OTP, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"TC58CVG0S3HxAIx", { .id = { 0x98, 0xC2, 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_STD_E, HI_SPI_NAND_CMD_READ, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_STD_E, HI_SPI_NAND_CMD_PP, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_EN, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x0, .hi_status_feature_reg = 0x0, {0} }, {"F35SQA002G", { .id = { 0xCD, 0x72, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 3, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"F35SQA001G", { .id = { 0xCD, 0x71, 0x71, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_128, .erasesize = SZ_128K, .options = 0, .id_len = 3, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"XT26G02CWSIGA", { .id = { 0x0B, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 64, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"XT26G00CWSIGA", { .id = { 0x0B, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_128, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"GD5F2GM7UExxG", { .id = { 0xC8, 0x92, 0xC8, 0x92, 0xFF, 0xFF, 0xFF, 0xFF } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 4, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"W25N02KV", { .id = { 0xEF, 0xAA, 0x22, 0x00, 0x00, 0xFF, 0xFF, 0xFF } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 3, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x2, .hi_config_feature_reg = 0x8, .hi_status_feature_reg = 0x0, {0} }, {"35X2GBXXX", { .id = { 0xe5, 0xf2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"F2G24AD", { .id = { 0xC2, 0x14, 0x24, 0x35, 0x03, 0x00, 0x00, 0x00 } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 5, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_DIS, .hi_protect_feature_reg = 0x0, .hi_config_feature_reg = 0x1, .hi_status_feature_reg = 0x0, {0} }, {"S35ML02G3", { .id = { 0x01, 0x25, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } }, .pagesize = SZ_2K, .chipsize = SZ_256, .erasesize = SZ_128K, .options = 0, .id_len = 2, .oobsize = 128, NAND_ECC_INFO(8, SZ_1K), .nand_flash_type = HI_SPI_NAND_E, .read_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .write_addr_cycle = HI_NAND_ADDR_CYCLE_5_E, .erase_addr_cycle = HI_NAND_ADDR_CYCLE_3_E, .spi_nand_rw_cfg = { HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_READ_QUAD, HI_SPI_NAND_STD_READ_DUMMY_NUM, HI_SPI_NAND_QUADIN_QUADOUT_E, HI_SPI_NAND_CMD_WRITE_QUAD, HI_SPI_NAND_WRITE_DUMMY_NUM, {0} }, .hi_options = HI_NAND_INNER_ECC_EN, .hi_protect_feature_reg = 0x2, .hi_config_feature_reg = 0x10, .hi_status_feature_reg = 0x0, {0} }, #else /* * Some incompatible NAND chips share device ID's and so must be * listed by full ID. We list them first so that we can easily identify * the most specific match. */ {"TC58NVG0S3E 1G 3.3V 8-bit", { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), 2 }, {"TC58NVG2S0F 4G 3.3V 8-bit", { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} }, SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) }, {"TC58NVG2S0H 4G 3.3V 8-bit", { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00} }, SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) }, {"TC58NVG3S0F 8G 3.3V 8-bit", { .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} }, SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) }, {"TC58NVG5D2 32G 3.3V 8-bit", { .id = {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} }, SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, {"TC58NVG6D2 64G 3.3V 8-bit", { .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} }, SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, {"SDTNRGAMA 64G 3.3V 8-bit", { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, {"H27UBG8T2BTR-BC 32G 3.3V 8-bit", { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} }, SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, NAND_ECC_INFO(40, SZ_1K), 0 }, {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, NAND_ECC_INFO(40, SZ_1K), 4 }, {"H27QCG8T2E5R‐BCF 64G 3.3V 8-bit", { .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} }, SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664, NAND_ECC_INFO(56, SZ_1K), 1 }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 32MiB 1,8V 8-bit", 0x35, 32, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 32MiB 3,3V 8-bit", 0x75, 32, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 32MiB 1,8V 16-bit", 0x45, 32, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 32MiB 3,3V 16-bit", 0x55, 32, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 64MiB 1,8V 8-bit", 0x36, 64, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 64MiB 3,3V 8-bit", 0x76, 64, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 64MiB 1,8V 16-bit", 0x46, 64, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 64MiB 3,3V 16-bit", 0x56, 64, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x78, 128, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x39, 128, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 128MiB 3,3V 8-bit", 0x79, 128, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x72, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x49, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x74, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x59, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND("NAND 256MiB 3,3V 8-bit", 0x71, 256, SZ_16K, SP_OPTIONS), /* * These are the new chips with large page size. Their page size and * eraseblock size are determined from the extended ID bytes. */ /* 512 Megabit */ EXTENDED_ID_NAND("NAND 64MiB 1,8V 8-bit", 0xA2, 64, LP_OPTIONS), EXTENDED_ID_NAND("NAND 64MiB 1,8V 8-bit", 0xA0, 64, LP_OPTIONS), EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xF2, 64, LP_OPTIONS), EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xD0, 64, LP_OPTIONS), EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xF0, 64, LP_OPTIONS), EXTENDED_ID_NAND("NAND 64MiB 1,8V 16-bit", 0xB2, 64, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 64MiB 1,8V 16-bit", 0xB0, 64, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 64MiB 3,3V 16-bit", 0xC2, 64, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 64MiB 3,3V 16-bit", 0xC0, 64, LP_OPTIONS16), /* 1 Gigabit */ EXTENDED_ID_NAND("NAND 128MiB 1,8V 8-bit", 0xA1, 128, LP_OPTIONS), EXTENDED_ID_NAND("NAND 128MiB 3,3V 8-bit", 0xF1, 128, LP_OPTIONS), EXTENDED_ID_NAND("NAND 128MiB 3,3V 8-bit", 0xD1, 128, LP_OPTIONS), EXTENDED_ID_NAND("NAND 128MiB 1,8V 16-bit", 0xB1, 128, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 128MiB 3,3V 16-bit", 0xC1, 128, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 128MiB 1,8V 16-bit", 0xAD, 128, LP_OPTIONS16), /* 2 Gigabit */ EXTENDED_ID_NAND("NAND 256MiB 1,8V 8-bit", 0xAA, 256, LP_OPTIONS), EXTENDED_ID_NAND("NAND 256MiB 3,3V 8-bit", 0xDA, 256, LP_OPTIONS), EXTENDED_ID_NAND("NAND 256MiB 1,8V 16-bit", 0xBA, 256, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 256MiB 3,3V 16-bit", 0xCA, 256, LP_OPTIONS16), /* 4 Gigabit */ EXTENDED_ID_NAND("NAND 512MiB 1,8V 8-bit", 0xAC, 512, LP_OPTIONS), EXTENDED_ID_NAND("NAND 512MiB 3,3V 8-bit", 0xDC, 512, LP_OPTIONS), EXTENDED_ID_NAND("NAND 512MiB 1,8V 16-bit", 0xBC, 512, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 512MiB 3,3V 16-bit", 0xCC, 512, LP_OPTIONS16), /* 8 Gigabit */ EXTENDED_ID_NAND("NAND 1GiB 1,8V 8-bit", 0xA3, 1024, LP_OPTIONS), EXTENDED_ID_NAND("NAND 1GiB 3,3V 8-bit", 0xD3, 1024, LP_OPTIONS), EXTENDED_ID_NAND("NAND 1GiB 1,8V 16-bit", 0xB3, 1024, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 1GiB 3,3V 16-bit", 0xC3, 1024, LP_OPTIONS16), /* 16 Gigabit */ EXTENDED_ID_NAND("NAND 2GiB 1,8V 8-bit", 0xA5, 2048, LP_OPTIONS), EXTENDED_ID_NAND("NAND 2GiB 3,3V 8-bit", 0xD5, 2048, LP_OPTIONS), EXTENDED_ID_NAND("NAND 2GiB 1,8V 16-bit", 0xB5, 2048, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 2GiB 3,3V 16-bit", 0xC5, 2048, LP_OPTIONS16), /* 32 Gigabit */ EXTENDED_ID_NAND("NAND 4GiB 1,8V 8-bit", 0xA7, 4096, LP_OPTIONS), EXTENDED_ID_NAND("NAND 4GiB 3,3V 8-bit", 0xD7, 4096, LP_OPTIONS), EXTENDED_ID_NAND("NAND 4GiB 1,8V 16-bit", 0xB7, 4096, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 4GiB 3,3V 16-bit", 0xC7, 4096, LP_OPTIONS16), /* 64 Gigabit */ EXTENDED_ID_NAND("NAND 8GiB 1,8V 8-bit", 0xAE, 8192, LP_OPTIONS), EXTENDED_ID_NAND("NAND 8GiB 3,3V 8-bit", 0xDE, 8192, LP_OPTIONS), EXTENDED_ID_NAND("NAND 8GiB 1,8V 16-bit", 0xBE, 8192, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 8GiB 3,3V 16-bit", 0xCE, 8192, LP_OPTIONS16), /* 128 Gigabit */ EXTENDED_ID_NAND("NAND 16GiB 1,8V 8-bit", 0x1A, 16384, LP_OPTIONS), EXTENDED_ID_NAND("NAND 16GiB 3,3V 8-bit", 0x3A, 16384, LP_OPTIONS), EXTENDED_ID_NAND("NAND 16GiB 1,8V 16-bit", 0x2A, 16384, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 16GiB 3,3V 16-bit", 0x4A, 16384, LP_OPTIONS16), /* 256 Gigabit */ EXTENDED_ID_NAND("NAND 32GiB 1,8V 8-bit", 0x1C, 32768, LP_OPTIONS), EXTENDED_ID_NAND("NAND 32GiB 3,3V 8-bit", 0x3C, 32768, LP_OPTIONS), EXTENDED_ID_NAND("NAND 32GiB 1,8V 16-bit", 0x2C, 32768, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 32GiB 3,3V 16-bit", 0x4C, 32768, LP_OPTIONS16), /* 512 Gigabit */ EXTENDED_ID_NAND("NAND 64GiB 1,8V 8-bit", 0x1E, 65536, LP_OPTIONS), EXTENDED_ID_NAND("NAND 64GiB 3,3V 8-bit", 0x3E, 65536, LP_OPTIONS), EXTENDED_ID_NAND("NAND 64GiB 1,8V 16-bit", 0x2E, 65536, LP_OPTIONS16), EXTENDED_ID_NAND("NAND 64GiB 3,3V 16-bit", 0x4E, 65536, LP_OPTIONS16), #endif /* CONFIG_HSAN */ {NULL} }; /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba"}, {NAND_MFR_SAMSUNG, "Samsung"}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix"}, {NAND_MFR_MICRON, "Micron"}, {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, {NAND_MFR_SANDISK, "SanDisk"}, {NAND_MFR_INTEL, "Intel"}, {NAND_MFR_ATO, "ATO"}, {NAND_MFR_WINBOND, "Winbond"}, {NAND_MFR_GIGADEVICE,"GigaDevice"}, {0x0, "Unknown"} }; EXPORT_SYMBOL(nand_manuf_ids); EXPORT_SYMBOL(nand_flash_ids); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); MODULE_DESCRIPTION("Nand device & manufacturer IDs"); 如果我的flash型号是W25N02KV,那么我的block_size、page_size、oob_size、ecc_bit应该是多少?
最新发布
09-16
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