SOC 330: Media and SocietySQL

Java Python WELCOME TO SOC 330: Media and Society

Course description: This survey course is designed to introduce students to various intersections of mass media, popular culture, and society. Through a reading of some classic works targeting the intersection of media and society, students will explore questions such as: what factors determine the form and content of news media? What is propaganda and how does it function? In what ways has digitization reoriented traditional economic and social processes? Has the internet merely reinforced pre-existing social inequalities, or has it provided society with tools to overcome them? Our central objective is to equip ourselves with the necessary perspectives to analyze the flow of images and messages in political news, popular culture, and other realms of mass media(ted) communication.

Expected learning outcomes: This class is geared toward advanced students. Students are expected to understand major concepts and methods of inquiry social and behavioral scientists use to explore social, economic and political-cultural phenomena. In addition to building up a conceptual tool  kit, students will develop their analytic, methodological, and interpretive skills. Please note that this is a SBS+ (F-DEC) class and students are expected to engage with sociological materials at a deeper level.

Readings: Weekly readings will be posted on Brightspace each Monday. These readings will be related to the lectures. The purpose of my lectures is to make them more digestible for you.

Lectures: Each week there will be one or two lectures. The lectures will be posted on Monday.

Assignments: Your grade will be based on a combination of written engagement with sociological theories and two multiple-choice in-class exams. Please do not use ChatGPT.

Weekly reflections: Each week you will submit one (approximately) 350-word reflection. You should include references to at least one of the readings assigned that week. You may also reference previous weeks ifyou wish. In this reflection, you will discuss the readings and lectures with reference&nb SOC 330: Media and SocietySQL sp;to the weekly discussion prompt. The discussion prompt might be a question, a news article, a video, or some other form. of media. Prompts will be posted on Mondays. The purpose of this assignment is to check your reading comprehension. The weekly reflections are due on brightspace every Monday at midnight.

Final paper: The course will culminate in a ten-page (double-spaced) final paper in which you will be required to explore a topic ofyour choice via the application of one or more of the theoretical approaches covered this semester. The paper will be written in ASA format and will be submitted on Brightspace at midnight on the last day of class. In this paper you are expected to do the following:

1)   Introduce a social problem ofyour choice. Provide a brief background of the problem and explain why it is a social problem rather than a personal problem. This problem must be somehow related to one of the module themes.

2)   Summarize the theoretical perspective(s) ofyour choice. Clearly state the concepts you will be using and explain why they are suitable to analyze the problem.

3)   Apply the theory to imagine a solution to the problem. In an ideal world, what needs to happen socially, politically, and/or culturally to address this problem? What are the first steps?

4)   There is no requirement for the number of citations, but you should use outside citations as

necessary, especially when describing your chosen social problem. You must cite at least one of the scholars that we have covered this semester–more is not necessarily better.

Your paper should have a clear introduction which poses the social problem and conclusion which summarizes your argument. You will be evaluated primarily on the clarity ofyour argument and the accuracy and competency you demonstrate when applying your chosen theoretical perspective(s).

Exams: The exams will be multiple choice and are simply intended to hold you accountable for having done the required reading. All exams are cumulative         

我把用户空间内对soc的代码发给你,参考后修改这个驱动#include <sys/types.h> #include <sys/stat.h> #include <sys/types.h> #include <sys/stat.h> #include <sys/mman.h> #include <sys/ioctl.h> #include <fcntl.h> #include <unistd.h> #include <stdlib.h> #include <stdio.h> #include <errno.h> #include <string.h> #include "soc/soc.h" #include "soc/ioctl.h" #include "soc/sysinfo.h" #include "soc/busrw.h" #include "soc/egpio.h" #include "soc/vcxo.h" #define VCXO_1_CLK_IN 80000000 int soc::dev; uint16_t soc::version; uint16_t soc::devcode; uint32_t soc::clk_freq; double soc::clk_MHz; double soc::clk_MHz_div_65536; uint8_t soc::sclk_ratio_prescale; unsigned int soc::peri_base; unsigned int soc::mm_base; bool soc::flag_dma_mapped; unsigned int soc::flags; sysinfo_typedef* soc::sysinfo; euart_typedef* soc::chuart; mcbsp_typedef* soc::mcbsp; sclk_typedef* soc::sclk; busrw_typedef* soc::busrw; trig_typedef* soc::trig; pktdma_typedef* soc::pktdma; pack_typedef* soc::pack; ledspi_typedef* soc::ledspi; systime_typedef* soc::systime; vcxo_typedef* soc::vcxo; euart_typedef* soc::gpsuart; gps_typedef* soc::gps; euart_typedef* soc::pwruart; egpio_typedef* soc::egpio; espi_typedef* soc::espi0; espi_typedef* soc::espi1; espi_typedef* soc::espi2; espi_typedef* soc::espi3; espi_typedef* soc::espi4; espi_typedef* soc::espi5; espi_typedef* soc::espi6; espi_typedef* soc::espi7; espi_typedef* soc::bal_spi0; espi_typedef* soc::bal_spi1; busrw_ex_typedef* soc::busrw_ex; vcxo_typedef* soc::vcxo_1; static int map_peripherals(); static void soc_chk_ver(uint16_t pid, uint8_t var); int soc_init(uint16_t pid, uint8_t var) { soc::flags = 0; soc::dev = open("/dev/dhsoc", O_RDWR); if(soc::dev < 0) { printf(APP_NAME": soc: Cannot open /dev/dhsoc: %s (errno=%d)\n", strerror(errno), errno); return -1; } if(map_peripherals() < 0) { printf(APP_NAME": soc: deinit.\n"); soc_deinit(); return -1; } printf(APP_NAME": About to read sysinfo at 0x%08x\n", soc::peri_base + SYSINFO_OFFSET); soc::version = sysinfo_version(soc::sysinfo); soc::devcode = sysinfo_device(soc::sysinfo); printf(APP_NAME": soc version: 0x%x\n", (uint32_t)soc::version); // printf(APP_NAME": soc devcode: 0x%x\n", (uint32_t)soc::devcode); soc_chk_ver(pid, var); busrw_close(soc::busrw); // Call busrw_close to init channel map RAM sysinfo_set_busrw_type(soc::sysinfo, 0); return 0; } void soc_deinit() { if(soc::peri_base) { munmap((void *)(soc::peri_base), DHSOC_PERI_REGION); soc::peri_base = 0; } if(soc::mm_base) { munmap((void *)(soc::mm_base), DMA_MEM_REGION); soc::mm_base = 0; } if(soc::dev) { close(soc::dev); } } bool soc_clk80m_alt_pll_locked() { return egpio_read_pin(soc::egpio) & EGPIO_IN_CLK80M_ALT_PLL_LOCKED; } static int map_peripherals() { soc::peri_base = (unsigned int) mmap(0, DHSOC_PERI_REGION, PROT_READ | PROT_WRITE, MAP_SHARED, soc::dev, LW_H2F_BASE); printf(APP_NAME": soc: mmap peri_base success.\n"); soc::mm_base = (unsigned int) mmap(0, DMA_MEM_REGION, PROT_READ | PROT_WRITE, MAP_SHARED, soc::dev, DMA_MEM_BASE); printf(APP_NAME": soc: mmap mm_base success.\n"); printf("DEBUG: peri_base = 0x%08x, mm_base = 0x%08x\n", soc::peri_base, soc::mm_base); if( (!soc::peri_base) || (!soc::mm_base) ) { printf(APP_NAME": soc: mmap failed.\n"); return -1; } soc::flag_dma_mapped = true; soc::sysinfo = (sysinfo_typedef *) (soc::peri_base + SYSINFO_OFFSET); soc::chuart = (euart_typedef *) (soc::peri_base + CHUART_OFFSET); soc::mcbsp = (mcbsp_typedef *) (soc::peri_base + MCBSP_OFFSET); soc::sclk = (sclk_typedef *) (soc::peri_base + SCLKCTRL_OFFSET); soc::busrw = (busrw_typedef *) (soc::peri_base + BUSRW_OFFSET); soc::trig = (trig_typedef *) (soc::peri_base + TRIG_OFFSET); soc::pktdma = (pktdma_typedef *) (soc::peri_base + PKTDMA_OFFSET); soc::pack = (pack_typedef *) (soc::peri_base + PACK_OFFSET); soc::ledspi = (ledspi_typedef *) (soc::peri_base + LEDSPI_OFFSET); soc::systime = (systime_typedef *) (soc::peri_base + SYSTIME_OFFSET); soc::vcxo = (vcxo_typedef *) (soc::peri_base + VCXO_OFFSET); soc::gpsuart = (euart_typedef *) (soc::peri_base + GPSUART_OFFSET); soc::gps = (gps_typedef *) (soc::peri_base + GPSSYNC_OFFSET); soc::pwruart = (euart_typedef *) (soc::peri_base + PWRUART_OFFSET); soc::egpio = (egpio_typedef *) (soc::peri_base + EGPIO_OFFSET); soc::espi0 = (espi_typedef *) (soc::peri_base + ESPI0_OFFSET); soc::busrw_ex = (busrw_ex_typedef *)(soc::peri_base + BUSRW_EX_OFFSET); soc::vcxo_1 = (vcxo_typedef *) (soc::peri_base + VCXO_1_OFFSET); soc::espi1 = (espi_typedef *) (soc::peri_base + ESPI1_OFFSET); soc::espi2 = (espi_typedef *) (soc::peri_base + ESPI2_OFFSET); soc::espi3 = (espi_typedef *) (soc::peri_base + ESPI3_OFFSET); soc::espi4 = (espi_typedef *) (soc::peri_base + ESPI4_OFFSET); soc::espi5 = (espi_typedef *) (soc::peri_base + ESPI5_OFFSET); soc::espi6 = (espi_typedef *) (soc::peri_base + ESPI6_OFFSET); soc::espi7 = (espi_typedef *) (soc::peri_base + ESPI7_OFFSET); soc::bal_spi0 = (espi_typedef *) (soc::peri_base + BAL_SPI0_OFFSET); soc::bal_spi1 = (espi_typedef *) (soc::peri_base + BAL_SPI1_OFFSET); printf(APP_NAME": soc: mmap success.\n"); return 0; } static void soc_chk_ver(uint16_t pid, uint8_t var) { // Default SoC configuration soc::clk_freq = SYS_CLK_v1; soc::clk_MHz = (double)soc::clk_freq * 0.000001; soc::clk_MHz_div_65536 = soc::clk_MHz * 0.0000152587890625; soc::sclk_ratio_prescale = 32; if( (pid == 0x5922) && ((var == 'N') || (var == 0)) ) { // Keep default config } else { // soc clock if(soc::version > 3) { soc::clk_freq = SYS_CLK_v4; soc::clk_MHz = (double)soc::clk_freq * 0.000001; soc::clk_MHz_div_65536 = soc::clk_MHz * 0.0000152587890625; } // re-sample ratio prescale if(soc::version > 4) { soc::sclk_ratio_prescale = 1; } // SoC module if(soc::version > 0xC) { soc::flags |= SOC_FLAG_SYSTIME_SUPPORT; } if(soc::version > 0xE) { soc::flags |= SOC_FLAG_GPSSYNC_SUPPORT; soc::flags |= SOC_FLAG_PWRUART_SUPPORT; } if(soc::version > 0x16) { if(soc_clk80m_alt_pll_locked()) { printf("vcxo 20M -> 80M is locked.\n"); } else { printf("vcxo 20M -> 80M is NOT locked.\n"); } soc::flags |= SOC_FLAG_VCXO_1_SUPPORT; soc::vcxo_1->fvcxo_l = (uint16_t)(VCXO_1_CLK_IN - 1); soc::vcxo_1->fvcxo_h = (uint16_t)((VCXO_1_CLK_IN - 1) >> 16); } } printf("\tSoC Sys Time Support: %c\n", (soc::flags & SOC_FLAG_SYSTIME_SUPPORT) ? 'Y' : 'N'); printf("\tSoC GPS Sync Support: %c\n", (soc::flags & SOC_FLAG_GPSSYNC_SUPPORT) ? 'Y' : 'N'); printf("\tSoC PWR UART Support: %c\n", (soc::flags & SOC_FLAG_PWRUART_SUPPORT) ? 'Y' : 'N'); printf("\tSoC VCXO(-1) Support: %c\n", (soc::flags & SOC_FLAG_VCXO_1_SUPPORT ) ? 'Y' : 'N'); } #ifndef SOC_H #define SOC_H #include "systype.h" /* system clock in HZ AND system clock in ns */ //#define SYS_CLK_HZ 51200000 //#define SYS_CLK_NS 20 // 19.53125 #define SYS_CLK_v1 51200000 #define SYS_CLK_v4 102400000 #define MCLK_20M (20 * 1000 * 1000) /* SoC peripheral/mm phy base & region */ #define LW_H2F_BASE 0xFF200000 #define DHSOC_PERI_REGION 4096 #define DMA_MEM_BASE (512 * 1024 * 1024) #define DMA_MEM_REGION (512 * 1024 * 1024) /* peripheral addr */ #define SYSINFO_OFFSET 0x00 #define CHUART_OFFSET 0x20 #define MCBSP_OFFSET 0x40 #define SCLKCTRL_OFFSET 0x60 #define BUSRW_OFFSET 0x80 #define TRIG_OFFSET 0xA0 #define PKTDMA_OFFSET 0xC0 #define PACK_OFFSET 0xE0 #define LEDSPI_OFFSET 0x100 #define SYSTIME_OFFSET 0x120 #define VCXO_OFFSET 0x140 #define GPSUART_OFFSET 0x160 #define GPSSYNC_OFFSET 0x180 #define PWRUART_OFFSET 0x1A0 #define EGPIO_OFFSET 0x1C0 #define ESPI0_OFFSET 0x1E0 #define BUSRW_EX_OFFSET 0x200 #define VCXO_1_OFFSET 0x220 #define ESPI1_OFFSET 0x240 #define ESPI2_OFFSET 0x260 #define ESPI3_OFFSET 0x280 #define ESPI4_OFFSET 0x2A0 #define ESPI5_OFFSET 0x2C0 #define ESPI6_OFFSET 0x2E0 #define ESPI7_OFFSET 0x300 #define BAL_SPI0_OFFSET 0x320 #define BAL_SPI1_OFFSET 0x340 #define EGPIO_IN_CLK80M_ALT_PLL_LOCKED (1 << 0) struct sysinfo_typedef; struct euart_typedef; struct mcbsp_typedef; struct sclk_typedef; struct busrw_typedef; struct trig_typedef; struct pktdma_typedef; struct pack_typedef; struct ledspi_typedef; struct systime_typedef; struct vcxo_typedef; struct gps_typedef; struct egpio_typedef; struct espi_typedef; struct busrw_ex_typedef; struct soc { static int dev; // my device static uint16_t version; // version static uint16_t devcode; // device code static uint32_t clk_freq; // system clock frequency static double clk_MHz; // system clock frequency in MHz static double clk_MHz_div_65536; // for systime usage static uint8_t sclk_ratio_prescale;// resample ratio prescale static unsigned int peri_base; // peri mmap base static unsigned int mm_base; // mm mmap base static uint32_t flags; // some flag static bool flag_dma_mapped; // dma mapped in driver static sysinfo_typedef *sysinfo; // PERI: system info static euart_typedef *chuart; // PERI: channel uart static mcbsp_typedef *mcbsp; // PERI: mcbsp static sclk_typedef *sclk; // PERI: sclkctrl static busrw_typedef *busrw; // PERI: busrw static trig_typedef *trig; // PERI: trig static pktdma_typedef *pktdma; // PERI: pktdma static pack_typedef *pack; // PERI: pack static ledspi_typedef *ledspi; // PERI: ledspi static systime_typedef *systime; // PERI: systime static vcxo_typedef *vcxo; // PERI: vcxo 0 static euart_typedef *gpsuart; // PERI: gps uart static gps_typedef *gps; // PERI: gps static euart_typedef *pwruart; // PERI: pwr uart static egpio_typedef *egpio; // PERI: egpio static espi_typedef *espi0; // PERI: espi static busrw_ex_typedef *busrw_ex; // PERI: busrw_ex static vcxo_typedef *vcxo_1; // PERI: vcxo 1 static espi_typedef *espi1; // PERI: espi static espi_typedef *espi2; // PERI: espi static espi_typedef *espi3; // PERI: espi static espi_typedef *espi4; // PERI: espi static espi_typedef *espi5; // PERI: espi static espi_typedef *espi6; // PERI: espi static espi_typedef *espi7; // PERI: espi static espi_typedef *bal_spi0; // PERI: espi static espi_typedef *bal_spi1; // PERI: espi }; #define SOC_FLAG_SYSTIME_SUPPORT (1 << 0) #define SOC_FLAG_GPSSYNC_SUPPORT (1 << 1) #define SOC_FLAG_PWRUART_SUPPORT (1 << 2) #define SOC_FLAG_VCXO_1_SUPPORT (1 << 3) int soc_init(uint16_t pid = 0x5922, uint8_t var = 'N'); void soc_deinit(void); bool soc_clk80m_alt_pll_locked(void); #endif // SOC_H #ifndef SOC_IOCTL_H #define SOC_IOCTL_H #define DHSOC_IOCTL_MAGIC 0x44 #define DHSOC_IOCTL_WXFERRST _IO(DHSOC_IOCTL_MAGIC, 0) #define DHSOC_IOCTL_GETWXFER _IO(DHSOC_IOCTL_MAGIC, 1) #define DHSOC_IOCTL_USER0CLK _IOW(DHSOC_IOCTL_MAGIC, 5, int) #define DHSOC_IOCTL_INVWXFER _IO(DHSOC_IOCTL_MAGIC, 6) #endif // SOC_IOCTL_H
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