Building Reliable and Efficint FPGA Designs

Adapt from Frank Nelson,the senior technical trainner  and course designer at Xilinx Inc.

1.Don't use gate clocks.

Don't route clock signals through the Look-Up Tables(LUTs).These "internally generated clock signals " can glitch easily.

Instead of routing this signal to the clock port of  the synchronous elements in the FPGA,route them to the clock enable port.

Not gating clocks also reduces the number of clock signals routed inside the FPGA.

If you do not have a  clock enable resource on each register ,this will be implemented as an input to the combinatorial  logic  driving the register(LUT).

2.Use the global routing resources

This reduces clock skew which makes the design more likely to run reliably.

Use the MaxSkew attribute in the UCF on control signals that are routed on general interconnect ,especially clocks.

3.Register Asynchronous input signals

This means signals which are not registered by the same clock frequency as the FPGA registers may need to be registered ,or use a synchronization circuit.

Consider using the IOB flip-flop to register your input.Note that these flip-flops often have variable set-up and hold times.

Synchronization circuits may also be necessary for transferring signals between clock domains within the FPGA.

Remember that synchronization circuits can prevent set-up and hold time violations on asynchronous inputs, which can cause failure of the circuit due to  metastability.

4 .Design with a synchronous Set/Reset.
Use of Asynchronous Set/Reset can easily create circuits that glitch.
Use the Global Set/Reset (GSR) resources in the older device families to reduce the skew on a set/reset.

Don’t  use the GSR in Virtex .  The GSR has too much delay and general interconnect will distribute this signal quickly.