HDLBits Lemmings3_hdlbits lemming 3-优快云博客

本文链接：https://blog.youkuaiyun.com/aulloncheung/article/details/123264523

该博客介绍了如何使用有限状态机来模拟 Lemmings 的行走、跌落和挖掘行为。Lemmings 在行走时可以被指示挖掘，当它们在地面上且不跌落时开始挖掘，直到到达另一侧并开始坠落。在此过程中，跌落优先于挖掘，挖掘优先于改变方向。代码示例展示了如何用 Verilog 实现这一行为，包括状态转换和输出逻辑。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

题目：

In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not falling), and will continue digging until it reaches the other side (ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking in its original direction once it hits ground again. As with falling, being bumped while digging has no effect, and being told to dig when falling or when there is no ground is ignored.

(In other words, a walking Lemming can fall, dig, or switch directions. If more than one of these conditions are satisfied, fall has higher precedence than dig, which has higher precedence than switching directions.)

Extend your finite state machine to model this behaviour.

状态图：

题目解释：

LEFT状态和DIG状态时，主要注意ground优先级高于dig高于bump；dig触发立马进入DIG_L或DIG_R状态；挖掘过程DIG_L，DIG_R以及掉落过程G_L，G_R只有ground触发有用。

代码：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    reg [2:0] state,state_next;
    parameter LEFT=0,RIGHT=1,DIG_L=2,DIG_R=3,G_L=4,G_R=5;
    reg [3:0] out;
    always @(posedge clk or posedge areset)
    begin
        if(areset)
            state <= LEFT;
        else
            state <= state_next;
    end
    
    always @(*)
        begin
            case(state)
                LEFT:  state_next= ground?(dig?DIG_L:(bump_left?RIGHT:LEFT)):G_L;
                RIGHT: state_next= ground?(dig?DIG_R:(bump_right?LEFT:RIGHT)):G_R;
                DIG_L: state_next= ground?DIG_L:G_L;
                DIG_R: state_next= ground?DIG_R:G_R;
                G_L:   state_next= ground?LEFT:G_L;
                G_R:   state_next= ground?RIGHT:G_R;
            endcase
        end
    always @(posedge clk or posedge areset) begin
        if(areset == 1'b1) begin
            out <= 4'b1000;
        end
        else begin
            case(state_next)
                LEFT   :out <= 4'b1000;
                RIGHT  :out <= 4'b0100;
                G_R    :out <= 4'b0010;
                G_L    :out <= 4'b0010;
                DIG_R  :out <= 4'b0001;
                DIG_L  :out <= 4'b0001;
                default:out <= 4'b1000;
            endcase
        end
    end
    assign {walk_left,walk_right,aaah,digging}=out;

endmodule