【System Verilog and UVM基础入门25】功能覆盖率的实现

 tdc_coverage.sv

让代码开口说话！！！

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`uvm_analysis_imp_decl(_in_monitor_export)
`uvm_analysis_imp_decl(_out_monitor_export)

class tdc_coverage extends uvm_component;
	`uvm_component_utils(tdc_coverage)
	tdc_config 	m_config;
	bit			m_is_covered;
	virtual		tdc_if vif;
	
	tdc_cfg_desc	reg_cfg;
	tdc_item		in_queue[$];
	tdc_item		out_queue[$];
	tdc_item		in_tr;
	tdc_item		out_tr;
	
	uvm_analysis_imp_in_monitor_export #(tdc_item, tdc_coverage) in_mon_anlysis_export;
	uvm_analysis_imp_out_monitor_export #(tdc_item, tdc_coverage) out_mon_anlysis_export;
	
	//add coverage group here 
	`include "cg_tdc_func.svh"
	extern function new(string name, uvm_component pare