远程FPGA虚拟实验平台用SystemVerilog HDL实现计数器和分频器

原理

计数器

本实验中，材料给出的计数器是二进制来分频的，就搞得还挺麻烦。

/** The input port is replaced with an internal signal **/
wire reset = PB[0]; 
wire clk;

/************* The logic of this experiment *************/
logic  [23:0] count;
always@(posedge CLOCK or posedge reset)
begin
    if(reset)
        count <=	0;
    else
        count <=	count+1;
end

assign clk = count[22];//2^23，详解见下方

logic [7:0]q;
always @ (posedge clk or posedge reset)
	if (reset)
		q <= 1;
	else
		q <= {
   
   q[6:0], q[7