【VHDL】半减器和全减器的设计

题目描述：

设计一位半减器，然后利用元件方法设计一位全减器

半减器源代码：

library ieee;
use ieee.std_logic_1164.all;
entity h_suber is
port ( x,y:in std_logic;
diff,s_out:out std_logic);
end;
architecture one of h_suber is
begin
process(x,y)
begin
diff <= x xor y;
s_out <= (not x) and y;
end process;
end; 

全减器源代码：（全减器的实现可以调用半减器的代码，所以要将他们放在同一工程文件下）

library ieee;
use ieee.std_logic_1164.all;
entity fullsub is
port (xin,yin,sub_in:in std_logic;
   diffr,sub_out:out std_logic);
end;
architecture one of fullsub is
component h_suber
port (x,y:in std_logic;
diff,s_out:out std_logic);
end component;
signal c,d,e:std_logic;
begin
u1:h_suber port map(x => xin,y => yin,diff => c,s_out => d);
u2:h_suber port map(x => c,y => sub_in,diff => diffr,s_out => e);
sub_out <= d or e;
end;

波形图如下：

半减器功能仿真图

 

 

 

半减器时序仿真图

 

 

全减器功能仿真图

 

 

 

全减器时序仿真图