verilog学习笔记——三段式状态机

• https://blog.youkuaiyun.com/jason_child/article/details/60466050
  

• 摩尔状态机的架构 
  

• 状态转换图 
  

• coding

module finite_fsm(
z_o,
clk,
Rst_n,
w_i
);
//输出端口
output z_o;

//输入端口
input clk;
input Rst_n;
input w_i;

//输出端口类型声明
reg z_o;

//参数声明
parameter IDLE = 2'b00;
parameter S0 = 2'b01;
parameter S1 = 2'b10;

//内部信号声明
reg[1:0] current_state;
reg[1:0] next_state;
//状态寄存器
always @ (posedge clk or negedge Rst_n) begin
    if(!Rst_n)
            current_state <= IDLE;
    else
        current_state <= next_state;
end
//次态的组合逻辑
always @ (w_i or current_state) begin
    case(current_state)
        IDLE：begin
                  if(w_i) next_state = S0;
                   else   next_state = IDLE;
              end
        S0:  begin
                    if(w_i) next_state = S1;
                    else    next_state = IDLE;
             end
        S1:  begin
                    if(w_i) next_state = S1;
                    else    next_state = IDLE;
             end
        default : next_state = 2'bxx;
   endcase
end
//输出逻辑
always @ (*) beign
    case(current)
        IDLE:  z_o = 1'b0;
        S0:    z_o = 1'b0;
        S1:    z_o = 1'b1;
        default:  z_0 = 1'b0;
    endcase
end
endmodule

• 关于三段式状态机的一点总结 
  1确定输入输出信号，及其类型（是wire还是reg）； 
  2声明内部信号，一般需要定义current_state和next_state； 
  3用3个always语句描述状态机;第一个用来次态和现态的转换，第二个always用于现态在输入情况下转换为次态的组合逻辑；第三个语句用于现态到输出的组合逻辑输出。