HDLBits——Vectorgates(总线门的处理)

本文介绍了一个电路设计,该电路接受两个3位输入,并计算这两个向量的位或运算、逻辑或运算以及两个向量的取反(NOT)。通过观察模拟波形,展示了位或运算与逻辑或运算之间的区别。

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Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

Bitwise vs. Logical Operators
Earlier, we mentioned that there are bitwise and logical versions of the various boolean operators (e.g., norgate). When using vectors, the distinction between the two operator types becomes important. A bitwise operation between two N-bit vectors replicates the operation for each bit of the vector and produces a N-bit output, while a logical operation treats the entire vector as a boolean value (true = non-zero, false = zero) and produces a 1-bit output.

Look at the simulation waveforms at how the bitwise-OR and logical-OR differ.
在这里插入图片描述

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise[2] = a[2] | b[2];
    assign out_or_bitwise[1] = a[1] | b[1];
    assign out_or_bitwise[0] = a[0] | b[0];
    assign out_or_logical = a[2]|a[1]|a[0] |b[2]|b[1]|b[0];
    assign out_not[5] = ~b[2];
    assign out_not[4] = ~b[1];
    assign out_not[3] = ~b[0];
    assign out_not[2] = ~a[2];
    assign out_not[1] = ~a[1];
    assign out_not[0] = ~a[0];
endmodule

本段代码中最应该提的就是assign out_or_logical = a[2]|a[1]|a[0] |b[2]|b[1]|b[0];这一句,本体原意是让我们判断a、b的十进制数是否全为0,而当a、b十进制数全为0的话,那么a、b对应的二进制数肯定也都是0,这样我们用连续或的形式可以解决。

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