【verilog】杭电-数电实验8 移位寄存器设计

转载于 2024-12-26 18:25:20 发布 · 136 阅读

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原文链接：https://github.com/XdpCs/HDU-computer-organization

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源代码

`timescale 1ns / 1ps

module sreg (
    input cr_,
    input cp,
    input [1:0] s,
    input Sr,
    Sl,
    input [7:0] D,
    output reg [7:0] Q
);
  always @(posedge cp or negedge cr_) begin
    if (!cr_) Q <= 8'b0;
    else begin
      case (s)
        2'b01:   Q <= {Sr, Q[7:1]};
        2'b10:   Q <= {Q[6:0], Sl};
        2'b11:   Q <= D;
        default: Q <= Q;
      endcase
    end
  end
endmodule

引脚

set_property IOSTANDARD LVCMOS18 [get_ports cp]
set_property IOSTANDARD LVCMOS18 [get_ports cr_]
set_property IOSTANDARD LVCMOS18 [get_ports Sl]
set_property IOSTANDARD LVCMOS18 [get_ports Sr]
set_property PULLTYPE PULLDOWN [get_ports cr_]
set_property PULLTYPE PULLDOWN [get_ports Sl]
set_property PULLTYPE PULLDOWN [get_ports Sr]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property PACKAGE_PIN R1 [get_ports {Q[7]}]
set_property PACKAGE_PIN P2 [get_ports {Q[6]}]
set_property PACKAGE_PIN P1 [get_ports {Q[5]}]
set_property PACKAGE_PIN N2 [get_ports {Q[4]}]
set_property PACKAGE_PIN M1 [get_ports {Q[3]}]
set_property PACKAGE_PIN M2 [get_ports {Q[2]}]
set_property PACKAGE_PIN L1 [get_ports {Q[1]}]
set_property PACKAGE_PIN J2 [get_ports {Q[0]}]
set_property PACKAGE_PIN R4 [get_ports cp]
set_property PACKAGE_PIN T3 [get_ports cr_]
set_property PACKAGE_PIN U3 [get_ports {s[1]}]
set_property PACKAGE_PIN T4 [get_ports {s[0]}]
set_property PACKAGE_PIN V3 [get_ports Sl]
set_property PACKAGE_PIN V4 [get_ports Sr]
set_property PACKAGE_PIN W4 [get_ports {D[7]}]
set_property PACKAGE_PIN Y4 [get_ports {D[6]}]
set_property PACKAGE_PIN Y6 [get_ports {D[5]}]
set_property PACKAGE_PIN W7 [get_ports {D[4]}]
set_property PACKAGE_PIN Y8 [get_ports {D[3]}]
set_property PACKAGE_PIN Y7 [get_ports {D[2]}]
set_property PACKAGE_PIN T1 [get_ports {D[1]}]
set_property PACKAGE_PIN U1 [get_ports {D[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {D[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {s[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {s[0]}]
set_property PULLTYPE PULLDOWN [get_ports {D[7]}]
set_property PULLTYPE PULLDOWN [get_ports {D[6]}]
set_property PULLTYPE PULLDOWN [get_ports {D[5]}]
set_property PULLTYPE PULLDOWN [get_ports {D[4]}]
set_property PULLTYPE PULLDOWN [get_ports {D[3]}]
set_property PULLTYPE PULLDOWN [get_ports {D[2]}]
set_property PULLTYPE PULLDOWN [get_ports {D[1]}]
set_property PULLTYPE PULLDOWN [get_ports {D[0]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[7]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[6]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[5]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[4]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[3]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[2]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[1]}]
set_property PULLTYPE PULLDOWN [get_ports {Q[0]}]
set_property PULLTYPE PULLDOWN [get_ports {s[1]}]
set_property PULLTYPE PULLDOWN [get_ports {s[0]}]
set_property PULLTYPE PULLDOWN [get_ports cp]
set_property DEDICATED_ROUTE FALSE [get_nets cp]
set_property DEDICATED_ROUTE FALSE [get_nets cr_]

仿真

`timescale 1ns / 1ps

// 定义测试模块，通常以被测试模块名加"_tb"作为模块名，方便识别
module sim();

    // 声明与被测试的sreg模块端口对应的信号，输入信号定义为reg类型，以便在测试中赋值改变
    reg cr_bar;
    reg cp;
    reg [1:0] s;
    reg Sr;
    reg Sl;
    reg [7:0] D;
    // 输出信号定义为wire类型（这里原模块输出为reg类型，实际连接用wire接收其输出）
    wire [7:0] Q;

    // 实例化被测试的sreg模块，将测试模块中的对应信号连接到sreg模块的各个端口
    sreg dut (
       .cr_(cr_bar),
       .cp(cp),
       .s(s),
       .Sr(Sr),
       .Sl(Sl),
       .D(D),
       .Q(Q)
    );

    // 产生时钟信号的always块，设置时钟周期为10ns，可根据实际需求调整周期大小
    always #5 cp = ~cp;

    // 初始化块，用于设置初始状态以及执行整个仿真过程中的各种测试操作
    initial begin
        // 初始化所有输入信号
        cr_bar = 1;
        cp = 0;
        s = 2'b00;
        Sr = 0;
        Sl = 0;
        D = 8'b00000000;

        // 等待一段时间（这里等待10ns），让初始状态稳定
        #10;

        // 测试异步复位功能
        cr_bar = 0;
        #20;
        cr_bar = 1;
        #20;

        // 测试左移功能
        s = 2'b10;
        Sl = 1;
        #20;
        Sl = 0;
        #20;

        // 测试右移功能
        s = 2'b01;
        Sr = 1;
        #20;
        Sr = 0;
        #20;

        // 测试并行加载功能
        s = 2'b11;
        D = 8'b11110000;
        #20;

        // 测试不同控制信号组合情况
        s = 2'b00;
        #20;
        s = 2'b10;
        Sr = 1;
        #20;

        // 可以继续添加更多复杂的测试情况，如频繁切换控制信号、多次改变输入数据等
        // 例如，再进行一轮不同功能切换的测试
        s = 2'b11;
        D = 8'b01010101;
        #20;
        s = 2'b01;
        Sr = 0;
        #20;
        s = 2'b10;
        Sl = 1;
        #20;

        // 结束仿真
        $finish;
    end

endmodule