基于vhdl设计的各种功能的计数器源代码

最新推荐文章于 2024-05-21 11:10:05 发布

GJZGRB

最新推荐文章于 2024-05-21 11:10:05 发布

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文章标签： fpga开发嵌入式硬件算法 java 单片机

本文链接：https://blog.youkuaiyun.com/GJZGRB/article/details/138694831

Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;

ENTITY counters IS

   PORT
   (
       d       : IN    INTEGER RANGE 0 TO 255;
       clk       : IN   BIT;
       clear   : IN   BIT;
       ld       : IN   BIT;
       enable   : IN   BIT;
       up_down   : IN   BIT;
       qa       : OUT    INTEGER RANGE 0 TO 255;
       qb       : OUT    INTEGER RANGE 0 TO 255;
       qc       : OUT    INTEGER RANGE 0 TO 255;
       qd       : OUT    INTEGER RANGE 0 TO 255;
       qe       : OUT    INTEGER RANGE 0 TO 255;
       qf       : OUT    INTEGER RANGE 0 TO 255;
       qg       : OUT    INTEGER RANGE 0 TO 255;
       qh       : OUT    INTEGER RANGE 0 TO 255;
       qi       : OUT    INTEGER RANGE 0 TO 255;
       qj       : OUT    INTEGER RANGE 0 TO 255;
       qk       : OUT    INTEGER RANGE 0 TO 255;
       ql       : OUT    INTEGER RANGE 0 TO 255;
       qm       : OUT    INTEGER RANGE 0 TO 255;
       qn       : OUT    INTEGER RANGE 0 TO 255
   );

END counters;

ARCHITECTURE a OF counters IS
BEGIN
   -- An enable counter
   PROCESS (clk)
       VARIABLE   cnt           : INTEGER RANGE 0 TO 255;
   BEGIN
       IF (clk'EVENT AND clk = '1') THEN
           IF enable = '1' THEN
               cnt := cnt + 1;
           END IF;
       END IF;

       qa   <= cnt;

END PROCESS;

   -- A synchronous load counter
   PROCESS (clk)
       VARIABLE   cnt           : INTEGER RANGE 0 TO 255;
   BEGIN
       IF (clk'EVENT AND clk = '1') THEN
           IF ld = '0' THEN
               cnt := d;
     &