#define ADDRESS_ALIGN(address,align) (void *)(((uint64_t)address + align - 1) & (~(align - 1)))怎么解释?

这个宏定义ADDRESS_ALIGN的目的是将一个给定的地址按照特定的对齐方式进行对齐。对齐通常用于内存操作,以保证地址符合某种特定的边界要求(如页边界),从而提升性能或符合硬件要求。

以下是对这个宏的详细解释:

#define ADDRESS_ALIGN(address,align)  (void *)(((uint64_t)address + align - 1) & (~(align - 1)))

(uint64_t)address: 这部分将address转换为 64 位无符号整数类型uint64_t。这样做是为了确保地址计算在64位范围内进行,适用于现代计算平台。

align: 这是希望对齐的字节数。通常是2的幂,比如4096(通常用于页对齐)。

address + align - 1: 这部分的目的是为了确保地址向上对齐。例如,如果 address本身已经是对齐的,则不会有影响;如果没有对齐,则通过加上align - 1 确保它“超出”下一个对齐边界,然后通过接下来的位操作进行对齐。

~(align - 1): 这部分生成一个掩码,用于清除不需要的低位。假设align是4096,那么align - 1是4095(即 `0xFFF`),而~0xFFF则是0xFFFFF000,用于清除掉低12位。

(((uint64_t)address + align - 1) & (~(align - 1))): 这一部分是关键,它通过与掩码进行按位与操作,将地址对齐到align的边界。

(void *): 最终的强制类型转换,将结果转换为void * 类型,表明这是一个通用指针。

总结来说,这个宏通过将地址向上调整到最近的align倍数来实现地址对齐。它是一个常用的技巧,特别是在需要满足硬件对齐要求或优化内存访问时。

#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; <h> Flash Configuration ; <o0> Flash Base Address <0x0-0xFFFFFFFF:8> ; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ #define _ER_ROM_BASE 0x18000000 #define _ER_ROM_SIZE 0x00007FF8 // 32k - 8Byte ; Flash #define __ROM_BASE 0x01000000 #define __ROM_SIZE 0x00010000 ; Flash #define __ROM2_BASE 0x01000000 #define __ROM2_SIZE 0x00010000 /*--------------------- Embedded RAM Configuration --------------------------- ; <h> RAM Configuration ; <o0> RAM Base Address <0x0-0xFFFFFFFF:8> ; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00002000 // 8k /*--------------------- Stack / Heap Configuration --------------------------- ; <h> Stack / Heap Configuration ; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 // 1k #define __HEAP_SIZE 0x00000000 /*---------------------------------------------------------------------------- User Stack & Heap boundery definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE (__RAM_BASE ) #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) ; *(Veneer$$CMSE) ; uncomment for secure applications .ANY (+RO) .ANY (+XO) } ER_RAM _ER_ROM_BASE _ER_ROM_SIZE { ; load address = execution address OISV4AlgoLib.lib(+RO +XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } }我这个写的有什么问题吗
11-05
/* * Vhost-user RDMA device : init and packets forwarding * * Copyright (C) 2025 KylinSoft Inc. and/or its affiliates. All rights reserved. * * Author: Xiong Weimin <xiongweimin@kylinos.cn> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #ifndef VHOST_RDMA_QUEUE_H_ #define VHOST_RDMA_QUEUE_H_ #include <stdint.h> #include <stdbool.h> #include <linux/types.h> #include "vhost_rdma_ib.h" enum vhost_rdma_ib_wc_opcode { VHOST_RDMA_IB_WC_SEND, VHOST_RDMA_IB_WC_RDMA_WRITE, VHOST_RDMA_IB_WC_RDMA_READ, VHOST_RDMA_IB_WC_RECV, VHOST_RDMA_IB_WC_RECV_RDMA_WITH_IMM, }; enum vhost_rdma_ib_wc_status { /* Operation completed successfully */ VHOST_RDMA_IB_WC_SUCCESS, /* Local Length Error */ VHOST_RDMA_IB_WC_LOC_LEN_ERR, /* Local QP Operation Error */ VHOST_RDMA_IB_WC_LOC_QP_OP_ERR, /* Local Protection Error */ VHOST_RDMA_IB_WC_LOC_PROT_ERR, /* Work Request Flushed Error */ VHOST_RDMA_IB_WC_WR_FLUSH_ERR, /* Bad Response Error */ VHOST_RDMA_IB_WC_BAD_RESP_ERR, /* Local Access Error */ VHOST_RDMA_IB_WC_LOC_ACCESS_ERR, /* Remote Invalid Request Error */ VHOST_RDMA_IB_WC_REM_INV_REQ_ERR, /* Remote Access Error */ VHOST_RDMA_IB_WC_REM_ACCESS_ERR, /* Remote Operation Error */ VHOST_RDMA_IB_WC_REM_OP_ERR, /* Transport Retry Counter Exceeded */ VHOST_RDMA_IB_WC_RETRY_EXC_ERR, /* RNR Retry Counter Exceeded */ VHOST_RDMA_IB_WC_RNR_RETRY_EXC_ERR, /* Remote Aborted Error */ VHOST_RDMA_IB_WC_REM_ABORT_ERR, /* Fatal Error */ VHOST_RDMA_IB_WC_FATAL_ERR, /* Response Timeout Error */ VHOST_RDMA_IB_WC_RESP_TIMEOUT_ERR, /* General Error */ VHOST_RDMA_IB_WC_GENERAL_ERR }; enum vhost_rdma_ib_wr_opcode { VHOST_RDMA_IB_WR_RDMA_WRITE, VHOST_RDMA_IB_WR_RDMA_WRITE_WITH_IMM, VHOST_RDMA_IB_WR_SEND, VHOST_RDMA_IB_WR_SEND_WITH_IMM, VHOST_RDMA_IB_WR_RDMA_READ, }; enum vhost_rdma_queue_type { VHOST_RDMA_QUEUE_SQ, VHOST_RDMA_QUEUE_RQ, }; struct vhost_rdma_sq_req { union { /* Length of sg_list */ __le32 num_sge; /* Length of inline data */ __le16 inline_len; }; /* Flags of the WR properties */ __u8 send_flags; /* WR opcode, enum vhost_rdma_ib_wr_opcode */ __u32 opcode; /* User defined WR ID */ __le64 wr_id; #define VHOST_RDMA_IB_SEND_FENCE (1 << 0) #define VHOST_RDMA_IB_SEND_SIGNALED (1 << 1) #define VHOST_RDMA_IB_SEND_SOLICITED (1 << 2) #define VHOST_RDMA_IB_SEND_INLINE (1 << 3) /* Immediate data (in network byte order) to send */ __le32 imm_data; union { __le32 imm_data; __u32 invalidate_rkey; } ex; union { struct { /* Start address of remote memory buffer */ __le64 remote_addr; /* Key of the remote MR */ __le32 rkey; } rdma; struct { __u64 remote_addr; __u64 compare_add; __u64 swap; __u32 rkey; } atomic; struct { /* Index of the destination QP */ __le32 remote_qpn; /* Q_Key of the destination QP */ __le32 remote_qkey; /* Address Handle */ __le32 ah; } ud; /* Reserved for future */ __le64 reserved[4]; }; /* Inline data */ //__u8 inline_data[512]; /* Reserved for future */ __le32 reserved2[3]; /* Scatter/gather list */ struct vhost_rdma_sge sg_list[]; }; struct vhost_rdma_rq_req { __le32 qpn; /* Length of sg_list */ __le32 num_sge; /* User defined WR ID */ __le64 wr_id; /* Scatter/gather list */ struct vhost_rdma_sge sg_list[]; }; struct vhost_rdma_dma_info { uint32_t length; uint32_t resid; uint32_t cur_sge; uint32_t num_sge; uint32_t sge_offset; uint32_t reserved; union { uint8_t *inline_data; struct vhost_rdma_sge *sge; void *raw; }; }; struct vhost_rdma_send_wqe { struct vhost_rdma_sq_req *wr; struct vhost_rdma_av av; __u32 status; __u32 state; __aligned_u64 iova; __u32 mask; __u32 first_psn; __u32 last_psn; __u32 ack_length; __u32 ssn; __u32 has_rd_atomic; struct vhost_rdma_dma_info dma; }; struct vhost_rdma_cq_req { /* User defined WR ID */ __le64 wr_id; /* Work completion status, enum virtio_ib_wc_status */ __u8 status; /* WR opcode, enum virtio_ib_wc_opcode */ __u8 opcode; /* Padding */ __le16 padding; /* Vendor error */ __le32 vendor_err; /* Number of bytes transferred */ __le32 byte_len; /* Immediate data (in network byte order) to send */ __le32 imm_data; /* Local QP number of completed WR */ __le32 qp_num; /* Source QP number (remote QP number) of completed WR (valid only for UD QPs) */ __le32 src_qp; #define VHOST_RDMA_IB_WC_GRH (1 << 0) #define VHOST_RDMA_WC_WITH_IMM (1 << 1) /* Work completion flag */ __le32 wc_flags; /* Reserved for future */ __le32 reserved[3]; }; void init_send_wqe(struct vhost_rdma_qp *qp, struct vhost_rdma_sq_req *wr, unsigned int mask, unsigned int length, struct vhost_rdma_send_wqe *wqe); void vhost_rdma_handle_sq(void *arg); void vhost_rdma_handle_rq(__rte_unused void *arg); int vhost_rdma_cq_post(struct vhost_rdma_device *dev, struct vhost_rdma_cq *cq, struct vhost_rdma_cq_req *cqe, int solicited); int vhost_rdma_queue_init(struct vhost_rdma_qp *qp, struct vhost_rdma_queue* queue, const char* name, struct vhost_user_queue* vq, size_t elem_size, enum vhost_rdma_queue_type type); void vhost_rdma_queue_cleanup(struct vhost_rdma_qp *qp, struct vhost_rdma_queue* queue); #endif 添加英文注释
10-12
/** ****************************************************************************** * @file stm32f10x_dac.c * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file provides all the DAC firmware functions. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_dac.h" #include "stm32f10x_rcc.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @defgroup DAC * @brief DAC driver modules * @{ */ /** @defgroup DAC_Private_TypesDefinitions * @{ */ /** * @} */ /** @defgroup DAC_Private_Defines * @{ */ /* CR register Mask */ #define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* DAC Dual Channels SWTRIG masks */ #define DUAL_SWTRIG_SET ((uint32_t)0x00000003) #define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /* DHR registers offsets */ #define DHR12R1_OFFSET ((uint32_t)0x00000008) #define DHR12R2_OFFSET ((uint32_t)0x00000014) #define DHR12RD_OFFSET ((uint32_t)0x00000020) /* DOR register offset */ #define DOR_OFFSET ((uint32_t)0x0000002C) /** * @} */ /** @defgroup DAC_Private_Macros * @{ */ /** * @} */ /** @defgroup DAC_Private_Variables * @{ */ /** * @} */ /** @defgroup D
06-09
这是user_setup.h里的文件,你帮我修改,把完整代码发我// USER DEFINED SETTINGS // Set driver type, fonts to be loaded, pins used and SPI control method etc. // // See the User_Setup_Select.h file if you wish to be able to define multiple // setups and then easily select which setup file is used by the compiler. // // If this file is edited correctly then all the library example sketches should // run without the need to make any more changes for a particular hardware setup! // Note that some sketches are designed for a particular TFT pixel width/height // User defined information reported by "Read_User_Setup" test & diagnostics example #define USER_SETUP_INFO "User_Setup" // Define to disable all #warnings in library (can be put in User_Setup_Select.h) //#define DISABLE_ALL_LIBRARY_WARNINGS // ################################################################################## // // Section 1. Call up the right driver file and any options for it // // ################################################################################## // Define STM32 to invoke optimised processor support (only for STM32) //#define STM32 // Defining the STM32 board allows the library to optimise the performance // for UNO compatible "MCUfriend" style shields //#define NUCLEO_64_TFT //#define NUCLEO_144_TFT // STM32 8-bit parallel only: // If STN32 Port A or B pins 0-7 are used for 8-bit parallel data bus bits 0-7 // then this will improve rendering performance by a factor of ~8x //#define STM_PORTA_DATA_BUS //#define STM_PORTB_DATA_BUS // Tell the library to use parallel mode (otherwise SPI is assumed) //#define TFT_PARALLEL_8_BIT //#defined TFT_PARALLEL_16_BIT // **** 16-bit parallel ONLY for RP2040 processor **** // Display type - only define if RPi display //#define RPI_DISPLAY_TYPE // 20MHz maximum SPI // Only define one driver, the other ones must be commented out #define ILI9341_DRIVER // Generic driver for common displays //#define ILI9341_2_DRIVER // Alternative ILI9341 driver, see https://github.com/Bodmer/TFT_eSPI/issues/1172 //#define ST7735_DRIVER // Define additional parameters below for this display //#define ILI9163_DRIVER // Define additional parameters below for this display //#define S6D02A1_DRIVER //#define RPI_ILI9486_DRIVER // 20MHz maximum SPI //#define HX8357D_DRIVER //#define ILI9481_DRIVER //#define ILI9486_DRIVER //#define ILI9488_DRIVER // WARNING: Do not connect ILI9488 display SDO to MISO if other devices share the SPI bus (TFT SDO does NOT tristate when CS is high) //#define ST7789_DRIVER // Full configuration option, define additional parameters below for this display //#define ST7789_2_DRIVER // Minimal configuration option, define additional parameters below for this display //#define R61581_DRIVER //#define RM68140_DRIVER //#define ST7796_DRIVER //#define SSD1351_DRIVER //#define SSD1963_480_DRIVER //#define SSD1963_800_DRIVER //#define SSD1963_800ALT_DRIVER //#define ILI9225_DRIVER #define GC9A01_DRIVER // Some displays support SPI reads via the MISO pin, other displays have a single // bi-directional SDA pin and the library will try to read this via the MOSI line. // To use the SDA line for reading data from the TFT uncomment the following line: // #define TFT_SDA_READ // This option is for ESP32 ONLY, tested with ST7789 and GC9A01 display only // For ST7735, ST7789 and ILI9341 ONLY, define the colour order IF the blue and red are swapped on your display // Try ONE option at a time to find the correct colour order for your display // #define TFT_RGB_ORDER TFT_RGB // Colour order Red-Green-Blue // #define TFT_RGB_ORDER TFT_BGR // Colour order Blue-Green-Red // For M5Stack ESP32 module with integrated ILI9341 display ONLY, remove // in line below // #define M5STACK // For ST7789, ST7735, ILI9163 and GC9A01 ONLY, define the pixel width and height in portrait orientation // #define TFT_WIDTH 80 // #define TFT_WIDTH 128 // #define TFT_WIDTH 172 // ST7789 172 x 320 // #define TFT_WIDTH 170 // ST7789 170 x 320 // #define TFT_WIDTH 240 // ST7789 240 x 240 and 240 x 320 // #define TFT_HEIGHT 160 // #define TFT_HEIGHT 128 // #define TFT_HEIGHT 240 // ST7789 240 x 240 // #define TFT_HEIGHT 320 // ST7789 240 x 320 // #define TFT_HEIGHT 240 // GC9A01 240 x 240 // For ST7735 ONLY, define the type of display, originally this was based on the // colour of the tab on the screen protector film but this is not always true, so try // out the different options below if the screen does not display graphics correctly, // e.g. colours wrong, mirror images, or stray pixels at the edges. // Comment out ALL BUT ONE of these options for a ST7735 display driver, save this // this User_Setup file, then rebuild and upload the sketch to the board again: // #define ST7735_INITB // #define ST7735_GREENTAB // #define ST7735_GREENTAB2 // #define ST7735_GREENTAB3 // #define ST7735_GREENTAB128 // For 128 x 128 display // #define ST7735_GREENTAB160x80 // For 160 x 80 display (BGR, inverted, 26 offset) // #define ST7735_ROBOTLCD // For some RobotLCD Arduino shields (128x160, BGR, https://docs.arduino.cc/retired/getting-started-guides/TFT) // #define ST7735_REDTAB // #define ST7735_BLACKTAB // #define ST7735_REDTAB160x80 // For 160 x 80 display with 24 pixel offset // If colours are inverted (white shows as black) then uncomment one of the next // 2 lines try both options, one of the options should correct the inversion. // #define TFT_INVERSION_ON // #define TFT_INVERSION_OFF // ################################################################################## // // Section 2. Define the pins that are used to interface with the display here // // ################################################################################## // If a backlight control signal is available then define the TFT_BL pin in Section 2 // below. The backlight will be turned ON when tft.begin() is called, but the library // needs to know if the LEDs are ON with the pin HIGH or LOW. If the LEDs are to be // driven with a PWM signal or turned OFF/ON then this must be handled by the user // sketch. e.g. with digitalWrite(TFT_BL, LOW); // #define TFT_BL 32 // LED back-light control pin // #define TFT_BACKLIGHT_ON HIGH // Level to turn ON back-light (HIGH or LOW) // We must use hardware SPI, a minimum of 3 GPIO pins is needed. // Typical setup for ESP8266 NodeMCU ESP-12 is : // // Display SDO/MISO to NodeMCU pin D6 (or leave disconnected if not reading TFT) // Display LED to NodeMCU pin VIN (or 5V, see below) // Display SCK to NodeMCU pin D5 // Display SDI/MOSI to NodeMCU pin D7 // Display DC (RS/AO)to NodeMCU pin D3 // Display RESET to NodeMCU pin D4 (or RST, see below) // Display CS to NodeMCU pin D8 (or GND, see below) // Display GND to NodeMCU pin GND (0V) // Display VCC to NodeMCU 5V or 3.3V // // The TFT RESET pin can be connected to the NodeMCU RST pin or 3.3V to free up a control pin // // The DC (Data Command) pin may be labelled AO or RS (Register Select) // // With some displays such as the ILI9341 the TFT CS pin can be connected to GND if no more // SPI devices (e.g. an SD Card) are connected, in this case comment out the #define TFT_CS // line below so it is NOT defined. Other displays such at the ST7735 require the TFT CS pin // to be toggled during setup, so in these cases the TFT_CS line must be defined and connected. // // The NodeMCU D0 pin can be used for RST // // // Note: only some versions of the NodeMCU provide the USB 5V on the VIN pin // If 5V is not available at a pin you can use 3.3V but backlight brightness // will be lower. // ###### EDIT THE PIN NUMBERS IN THE LINES FOLLOWING TO SUIT YOUR ESP8266 SETUP ###### // For NodeMCU - use pin numbers in the form PIN_Dx where Dx is the NodeMCU pin designation /*#define TFT_MISO PIN_D6 // Automatically assigned with ESP8266 if not defined #define TFT_MOSI PIN_D7 // Automatically assigned with ESP8266 if not defined #define TFT_SCLK PIN_D5 // Automatically assigned with ESP8266 if not defined #define TFT_CS PIN_D8 // Chip select control pin D8 #define TFT_DC PIN_D3 // Data Command control pin #define TFT_RST PIN_D4 // Reset pin (could connect to NodeMCU RST, see next line)*/ //#define TFT_RST -1 // Set TFT_RST to -1 if the display RESET is connected to NodeMCU RST or 3.3V //#define TFT_BL PIN_D1 // LED back-light (only for ST7789 with backlight control pin) //#define TOUCH_CS PIN_D2 // Chip select pin (T_CS) of touch screen //#define TFT_WR PIN_D2 // Write strobe for modified Raspberry Pi TFT only // ###### FOR ESP8266 OVERLAP MODE EDIT THE PIN NUMBERS IN THE FOLLOWING LINES ###### // Overlap mode shares the ESP8266 FLASH SPI bus with the TFT so has a performance impact // but saves pins for other functions. It is best not to connect MISO as some displays // do not tristate that line when chip select is high! // Note: Only one SPI device can share the FLASH SPI lines, so a SPI touch controller // cannot be connected as well to the same SPI signals. // On NodeMCU 1.0 SD0=MISO, SD1=MOSI, CLK=SCLK to connect to TFT in overlap mode // On NodeMCU V3 S0 =MISO, S1 =MOSI, S2 =SCLK // In ESP8266 overlap mode the following must be defined //#define TFT_SPI_OVERLAP // In ESP8266 overlap mode the TFT chip select MUST connect to pin D3 //#define TFT_CS PIN_D3 //#define TFT_DC PIN_D5 // Data Command control pin //#define TFT_RST PIN_D4 // Reset pin (could connect to NodeMCU RST, see next line) //#define TFT_RST -1 // Set TFT_RST to -1 if the display RESET is connected to NodeMCU RST or 3.3V // ###### EDIT THE PIN NUMBERS IN THE LINES FOLLOWING TO SUIT YOUR ESP32 SETUP ###### // For ESP32 Dev board (only tested with ILI9341 display) // The hardware SPI can be mapped to any pins //#define TFT_MISO 19 //#define TFT_MOSI 23 //#define TFT_SCLK 18 //#define TFT_CS 15 // Chip select control pin //#define TFT_DC 2 // Data Command control pin //#define TFT_RST 4 // Reset pin (could connect to RST pin) //#define TFT_RST -1 // Set TFT_RST to -1 if display RESET is connected to ESP32 board RST // For ESP32 Dev board (only tested with GC9A01 display) // The hardware SPI can be mapped to any pins #define TFT_MOSI 3 // In some display driver board, it might be written as "SDA" and so on. #define TFT_SCLK 2 #define TFT_CS 6 // Chip select control pin #define TFT_DC 10 // Data Command control pin #define TFT_RST 7 // Reset pin (could connect to Arduino RESET pin) //#define TFT_BL 22 // LED back-light //#define TOUCH_CS 21 // Chip select pin (T_CS) of touch screen //#define TFT_WR 22 // Write strobe for modified Raspberry Pi TFT only // For the M5Stack module use these #define lines //#define TFT_MISO 19 //#define TFT_MOSI 23 //#define TFT_SCLK 18 //#define TFT_CS 14 // Chip select control pin //#define TFT_DC 27 // Data Command control pin //#define TFT_RST 33 // Reset pin (could connect to Arduino RESET pin) //#define TFT_BL 32 // LED back-light (required for M5Stack) // ###### EDIT THE PINs BELOW TO SUIT YOUR ESP32 PARALLEL TFT SETUP ###### // The library supports 8-bit parallel TFTs with the ESP32, the pin // selection below is compatible with ESP32 boards in UNO format. // Wemos D32 boards need to be modified, see diagram in Tools folder. // Only ILI9481 and ILI9341 based displays have been tested! // Parallel bus is only supported for the STM32 and ESP32 // Example below is for ESP32 Parallel interface with UNO displays // Tell the library to use 8-bit parallel mode (otherwise SPI is assumed) //#define TFT_PARALLEL_8_BIT // The ESP32 and TFT the pins used for testing are: //#define TFT_CS 33 // Chip select control pin (library pulls permanently low //#define TFT_DC 15 // Data Command control pin - must use a pin in the range 0-31 //#define TFT_RST 32 // Reset pin, toggles on startup //#define TFT_WR 4 // Write strobe control pin - must use a pin in the range 0-31 //#define TFT_RD 2 // Read strobe control pin //#define TFT_D0 12 // Must use pins in the range 0-31 for the data bus //#define TFT_D1 13 // so a single register write sets/clears all bits. //#define TFT_D2 26 // Pins can be randomly assigned, this does not affect //#define TFT_D3 25 // TFT screen update performance. //#define TFT_D4 17 //#define TFT_D5 16 //#define TFT_D6 27 //#define TFT_D7 14 // ###### EDIT THE PINs BELOW TO SUIT YOUR STM32 SPI TFT SETUP ###### // The TFT can be connected to SPI port 1 or 2 //#define TFT_SPI_PORT 1 // SPI port 1 maximum clock rate is 55MHz //#define TFT_MOSI PA7 //#define TFT_MISO PA6 //#define TFT_SCLK PA5 //#define TFT_SPI_PORT 2 // SPI port 2 maximum clock rate is 27MHz //#define TFT_MOSI PB15 //#define TFT_MISO PB14 //#define TFT_SCLK PB13 // Can use Ardiuno pin references, arbitrary allocation, TFT_eSPI controls chip select //#define TFT_CS D5 // Chip select control pin to TFT CS //#define TFT_DC D6 // Data Command control pin to TFT DC (may be labelled RS = Register Select) //#define TFT_RST D7 // Reset pin to TFT RST (or RESET) // OR alternatively, we can use STM32 port reference names PXnn //#define TFT_CS PE11 // Nucleo-F767ZI equivalent of D5 //#define TFT_DC PE9 // Nucleo-F767ZI equivalent of D6 //#define TFT_RST PF13 // Nucleo-F767ZI equivalent of D7 //#define TFT_RST -1 // Set TFT_RST to -1 if the display RESET is connected to processor reset // Use an Arduino pin for initial testing as connecting to processor reset // may not work (pulse too short at power up?) // ################################################################################## // // Section 3. Define the fonts that are to be used here // // ################################################################################## // Comment out the #defines below with // to stop that font being loaded // The ESP8366 and ESP32 have plenty of memory so commenting out fonts is not // normally necessary. If all fonts are loaded the extra FLASH space required is // about 17Kbytes. To save FLASH space only enable the fonts you need! #define LOAD_GLCD // Font 1. Original Adafruit 8 pixel font needs ~1820 bytes in FLASH #define LOAD_FONT2 // Font 2. Small 16 pixel high font, needs ~3534 bytes in FLASH, 96 characters #define LOAD_FONT4 // Font 4. Medium 26 pixel high font, needs ~5848 bytes in FLASH, 96 characters #define LOAD_FONT6 // Font 6. Large 48 pixel font, needs ~2666 bytes in FLASH, only characters 1234567890:-.apm #define LOAD_FONT7 // Font 7. 7 segment 48 pixel font, needs ~2438 bytes in FLASH, only characters 1234567890:-. #define LOAD_FONT8 // Font 8. Large 75 pixel font needs ~3256 bytes in FLASH, only characters 1234567890:-. //#define LOAD_FONT8N // Font 8. Alternative to Font 8 above, slightly narrower, so 3 digits fit a 160 pixel TFT #define LOAD_GFXFF // FreeFonts. Include access to the 48 Adafruit_GFX free fonts FF1 to FF48 and custom fonts // Comment out the #define below to stop the SPIFFS filing system and smooth font code being loaded // this will save ~20kbytes of FLASH #define SMOOTH_FONT // ################################################################################## // // Section 4. Other options // // ################################################################################## // For RP2040 processor and SPI displays, uncomment the following line to use the PIO interface. //#define RP2040_PIO_SPI // Leave commented out to use standard RP2040 SPI port interface // For RP2040 processor and 8 or 16-bit parallel displays: // The parallel interface write cycle period is derived from a division of the CPU clock // speed so scales with the processor clock. This means that the divider ratio may need // to be increased when overclocking. It may also need to be adjusted dependant on the // display controller type (ILI94341, HX8357C etc.). If RP2040_PIO_CLK_DIV is not defined // the library will set default values which may not suit your display. // The display controller data sheet will specify the minimum write cycle period. The // controllers often work reliably for shorter periods, however if the period is too short // the display may not initialise or graphics will become corrupted. // PIO write cycle frequency = (CPU clock/(4 * RP2040_PIO_CLK_DIV)) //#define RP2040_PIO_CLK_DIV 1 // 32ns write cycle at 125MHz CPU clock //#define RP2040_PIO_CLK_DIV 2 // 64ns write cycle at 125MHz CPU clock //#define RP2040_PIO_CLK_DIV 3 // 96ns write cycle at 125MHz CPU clock // For the RP2040 processor define the SPI port channel used (default 0 if undefined) //#define TFT_SPI_PORT 1 // Set to 0 if SPI0 pins are used, or 1 if spi1 pins used // For the STM32 processor define the SPI port channel used (default 1 if undefined) //#define TFT_SPI_PORT 2 // Set to 1 for SPI port 1, or 2 for SPI port 2 // Define the SPI clock frequency, this affects the graphics rendering speed. Too // fast and the TFT driver will not keep up and display corruption appears. // With an ILI9341 display 40MHz works OK, 80MHz sometimes fails // With a ST7735 display more than 27MHz may not work (spurious pixels and lines) // With an ILI9163 display 27 MHz works OK. // #define SPI_FREQUENCY 1000000 // #define SPI_FREQUENCY 5000000 // #define SPI_FREQUENCY 10000000 // #define SPI_FREQUENCY 20000000 #define SPI_FREQUENCY 27000000 // #define SPI_FREQUENCY 40000000 // #define SPI_FREQUENCY 55000000 // STM32 SPI1 only (SPI2 maximum is 27MHz) // #define SPI_FREQUENCY 80000000 // Optional reduced SPI frequency for reading TFT #define SPI_READ_FREQUENCY 20000000 // The XPT2046 requires a lower SPI clock rate of 2.5MHz so we define that here: #define SPI_TOUCH_FREQUENCY 2500000 // The ESP32 has 2 free SPI ports i.e. VSPI and HSPI, the VSPI is the default. // If the VSPI port is in use and pins are not accessible (e.g. TTGO T-Beam) // then uncomment the following line: //#define USE_HSPI_PORT // Comment out the following #define if "SPI Transactions" do not need to be // supported. When commented out the code size will be smaller and sketches will // run slightly faster, so leave it commented out unless you need it! // Transaction support is needed to work with SD library but not needed with TFT_SdFat // Transaction support is required if other SPI devices are connected. // Transactions are automatically enabled by the library for an ESP32 (to use HAL mutex) // so changing it here has no effect // #define SUPPORT_TRANSACTIONS
09-26
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