AD9253 LVDS 高速ADC驱动开发

1、查阅AD9253器件手册

2、查阅Xilinx xapp524手册

3、该款ADC工作在125Msps下，14bit - 2Lane - 1frame 模式。

对应：data clock时钟为500M DDR mode。data line rate：1Gbps。frame clock：1/4 data clock

具体内容：下文的参考博客写的很清楚，我就不详细写了。参考博客clock align模块不完整，本文新增这个模块。

`timescale 1ns / 1ps

module bit_clk_align(
    input  i_clk_p,
    input  i_clk_n,
    input  i_clk_200m,
    input  i_reset,
    output o_bitclk_align_done,
    output o_bitclk_Monclk,
    output o_bitclk_Refclk

);

//------------------ variable declare ------------------
localparam PHASE_ADJ_FAILED  =  1; // 0: OK   1:FAILED

wire s_BitClk_MonClkOut;
wire s_BitClk_RefClkOut;
wire s_bitclk;
wire s_idelayctrl_rdy;
wire s_bitclk_align_ena;
wire s_IntBitClk;
wire [07:00]s_bitclk_para;
wire [04:00]s_cntvalueout;
reg  r_idelay_ce    = 1;
reg  r_idelay_inc   = 1;

reg  [3:0]r_clk_div_reset   = 4'hf;    // high active
wire s_clk_div_reset;
reg  r_phase_adj_status   = 0;
reg  r_bitclk_align_done   = 0;
reg  [03:00] r_adj_cnt = 0;
reg  [03:00] r_bitclk_align_state = 0;
reg  [01:00] s_iserdesout_dly_cnt = 0;



//------------------ main body of code ------------------
assign  o_bitclk_Monclk  =  s_BitClk_MonClkOut;
assign  o_bitclk_Refclk  =  s_BitClk_RefClkOut;

// generate iserdes reset
always@(posedge s_BitClk_RefClkOut)begin
    r_clk_div_reset   <= r_clk_div_reset   >> 1;
end
assign s_clk_div_reset = (|r_clk_div_reset);

//
// state:  adjust local clock phase align to input clk
//
assign s_bitclk_align_ena = s_idelayctrl_rdy && (~i_reset);
always@(posedge s_BitClk_RefClkOut)begin
    case(r_bitclk_align_state)
        0:begin
            r_idelay_ce  <= 0;
            r_idelay_inc <= 0;
            r_phase_adj_status <= 0;
            r_bitclk_align_done <= 0;
            
            if(s_bitclk_align_ena)begin
                r_bitclk_align_state <= 1;
            end
        end
        1:begin
            //wait iserdes Q8~Q1 output stablely
            r_idelay_ce  <= 0;
            r_idelay_inc <= 0;
            if(s_iserdesout_dly_cnt >= 2)begin
                s_iserdesout_dly_cnt <= 0;
                r_bitclk_align_state <= r_bitclk_align_state + 1;
            end
            else begin
                s_iserdesout_dly_cnt <= s_iserdesout_dly_cnt + 1;
            end
        end
        2:begin
            // se