xilinx 时钟问题

最新推荐文章于 2025-06-10 17:39:47 发布

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最新推荐文章于 2025-06-10 17:39:47 发布 · 1.8w 阅读

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#Xilinx #Vivado #FPGA

本文讨论了在Xilinx FPGA设计中遇到的时钟问题，包括时钟IOB与BUFGCTRL未放置在最佳位置的错误以及如何通过设置CLOCK_DEDICATED_ROUTE约束来解决。介绍了Xilinx芯片全局时钟资源的五种使用方法，并分享了四个演示示例，展示了如何正确使用时钟资源。同时，提到了引脚分配问题，强调了GC和CC引脚的区别，建议确保时钟信号正确连接到专用的时钟输入。

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xilinx 时钟问题：

ERROR:Place:1398 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock IOB component <cmos_pclk> is placed at site <W10>. The corresponding BUFGCTRL component <cmos_pclk_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y0>. The clock IO can use the fast path between the IOB and the Clock Buffer if the IOB is placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
< NET "cmos_pclk" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

遇到上面的问题是因为我们将外部输入的一个时钟管脚 cmos_pclk(摄像头输出给FPGA的像素时钟)分配到了一个普通的IO口上面，如果是zedboard专有时钟管脚 Y9就肯定没这样的错误了。

因为是IO管脚上，所以其周围没有全局时钟 BUFG，所以我们在 XDC 里使用： NET "cmos_pclk" CLOCK_DEDICATED_ROUTE = FALSE; 来屏蔽 Xilinx 的检测，从而通过编译。