module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
always@(posedge clk)begin
if(reset)begin
ena <= 0;
end
else begin
if(q[3:0]==8)
ena[1]<=1;
else
ena[1]<=0;
if(q[3:0]==8&&q[7:4]==9)
ena[2]<=1;
else
ena[2]<=0;
if(q[3:0]==8&&q[7:4]==9&&q[11:8]==9)
ena[3]<=1;
else
ena[3]<=0;
end
end
autoAdder adder1(1, clk, reset, q[3:0]);
autoAdder adder2(ena[1], clk, reset, q[7:4]);
autoAdder adder3(ena[2], clk, reset, q[11:8]);
autoAdder adder4(ena[3], clk, reset, q[15:12]);
endmodule
module autoAdder(
input ena,
input clk,
input reset,
output [3:0]q
);
always@(posedge clk)begin
if(reset)begin
q <= 0;
end
else if(ena) begin
if(q==4'd9)
q<=0;
else
q <= q + 1;
end
else
q <= q;
end
endmodule