多应用程序编译，Makefile

最新推荐文章于 2024-10-25 11:02:34 发布

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最新推荐文章于 2024-10-25 11:02:34 发布

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分类专栏： Mikefile/bash 文章标签： makefile dependencies include compilation file object

本文链接：https://blog.youkuaiyun.com/zanget/article/details/7087590

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本文详细解析了Makefile文件的构建流程，包括其核心内容、关键信息以及信息技术领域的相关关键词。通过理解Makefile的基本语法和用法，读者可以更好地掌握如何设置Makefile以满足不同情况下的构建需求。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

CC=g++
TARGET=cppTest
OTHERDIR=../../someotherpath/in/project/src

SOURCE = cppTest.cpp
SOURCE = $(OTHERDIR)/file.cpp

## End sources definition
INCLUDE = -I./ $(AN_INCLUDE_DIR)  
INCLUDE = -I.$(OTHERDIR)/../inc
## end more includes

VPATH=$(OTHERDIR)
OBJ=$(join $(addsuffix ../obj/, $(dir $(SOURCE))), $(notdir $(SOURCE:.cpp=.o))) 

## Fix dependency destination to be ../.dep relative to the src dir
DEPENDS=$(join $(addsuffix ../.dep/, $(dir $(SOURCE))), $(notdir $(SOURCE:.cpp=.d)))

## Default rule executed
all: $(TARGET)
        @true

## Clean Rule
clean:
        @-rm -f $(TARGET) $(OBJ) $(DEPENDS)


## Rule for making the actual target
$(TARGET): $(OBJ)
        @echo "============="
        @echo "Linking the target $@"
        @echo "============="
        @$(CC) $(CFLAGS) -o $@ $^ $(LIBS)
        @echo -- Link finished --

## Generic compilation rule
%.o : %.cpp
        @mkdir -p $(dir $@)
        @echo "============="
        @echo "Compiling {1}lt;"
        @$(CC) $(CFLAGS) -c {1}lt; -o $@


## Rules for object files from cpp files
## Object file for each file is put in obj directory
## one level up from the actual source directory.
../obj/%.o : %.cpp
        @mkdir -p $(dir $@)
        @echo "============="
        @echo "Compiling {1}lt;"
        @$(CC) $(CFLAGS) -c {1}lt; -o $@

# Rule for "other directory"  You will need one per "other" dir
$(OTHERDIR)/../obj/%.o : %.cpp
        @mkdir -p $(dir $@)
        @echo "============="
        @echo "Compiling {1}lt;"
        @$(CC) $(CFLAGS) -c {1}lt; -o $@

## Make dependancy rules
../.dep/%.d: %.cpp
        @mkdir -p $(dir $@)
        @echo "============="
        @echo Building dependencies file for $*.o
        @$(SHELL) -ec '$(CC) -M $(CFLAGS) {1}lt; | sed "s^$*.o^../obj/$*.o^" > $@'

## Dependency rule for "other" directory
$(OTHERDIR)/../.dep/%.d: %.cpp
        @mkdir -p $(dir $@)
        @echo "============="
        @echo Building dependencies file for $*.o
        @$(SHELL) -ec '$(CC) -M $(CFLAGS) {1}lt; | sed "s^$*.o^$(OTHERDIR)/../obj/$*.o^" > $@'

## Include the dependency files
-include $(DEPENDS)

参考Makefile语法

1.http://blog.youkuaiyun.com/yrj/article/details/4046853

2.http://locklessinc.com/articles/makefile_tricks/ 【very nice】

3.http://blog.chinaunix.net/space.php?uid=11278770&do=blog&id=148571

4.The best way to set up makefiles for various situations http://makepp.sourceforge.net/1.19/makepp_cookbook.html