yycya的博客

Verilog Modelsim仿真实验 打开Quartus II软件，点击File再点击New,选择Verilog FDL File,然后在空白处 输入代码：module add4(S,COUT,CIN,X,Y); output COUT; output [3:0] S; input CIN; input [3:0]X,Y; reg [3:0] S; reg COUT; always @(X ,Y, CIN) {COUT,S}=X+Y+CIN; endmodule module tb_41; w