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最新推荐文章于 2025-04-20 07:06:30 发布

yunhuang2010

最新推荐文章于 2025-04-20 07:06:30 发布

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分类专栏： Hardware Zed

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本文记录了使用 Xilinx ISE 14.2 对 ZedBoard 开发板进行部分重构验证的过程。验证涉及 led_a、led_b 和 black_box 三个模块，其中 led_b 模块验证成功，而 led_a 和 black_box 模块间存在 proxy 逻辑数量不匹配的问题，导致验证失败。

Release 14.2 - pr_verify P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Fri Dec 21 18:23:40 2012

Command Line: D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
-o
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/ISE/Led-B/pr_verify.log
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd

Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd: Fri Dec 21 17:42:54 2012
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd: Fri Dec 21 18:22:33 2012
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd: Fri Dec 21 18:22:32 2012

----------------------------------------
Analyzing Designs:

H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd

H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd

Number of matched proxy logic bels = 82
Number of matched external nets = 80
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0

Verification completed successfully!

----------------------------------------
Analyzing Designs:

H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd

H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd

ERROR:HDTools:30 - Found different numbers of proxy logic - 82/74.
Number of matched proxy logic bels = 0
Number of matched external nets = 0
Number of matched global clock nets = 0
Number of matched Reconfigurable Partitions = 0

VERIFICATION FAILED!

Verification completed with Errors.

----------------------------------------
Analyzing Designs:

H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd

H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd

ERROR:HDTools:30 - Found different numbers of proxy logic - 74/82.
Number of matched proxy logic bels = 0
Number of matched external nets = 0
Number of matched global clock nets = 0
Number of matched Reconfigurable Partitions = 0

VERIFICATION FAILED!

Verification completed with Errors.

D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd => FAIL