UVM学习记录1

记录一些UVM基础机制的学习。

编译UVM代码

• 编译文件uvm_compile.sv，在work库中simulate模块uvm_compile，执行run -all命令。

module uvm_compile;
  // 导入Questa预编译好的UVM库
  import uvm_pkg::*;
  `include "uvm_macros.svh"

  initial begin
    `uvm_info("UVM", "Hello, welcome to RKV UVM training!", UVM_LOW)
    #1us;
    `uvm_info("UVM", "Bye, and more gifts waiting for you!", UVM_LOW)
  end
endmodule

• SV与UVM之间的关系

编译仿真sv_class_inst.sv，仅在顶层module中例化顶层class top。

module sv_class_inst;

  import uvm_pkg::*;
  `include "uvm_macros.svh"

  class top;
    function new();
      `uvm_info("SV_TOP", "SV TOP creating", UVM_LOW)
    endfunction
  endclass

  initial begin
    top t; 
    `uvm_info("SV_TOP", "test started", UVM_LOW)
    t = new();
    `uvm_info("SV_TOP", "test finished", UVM_LOW)
  end

endmodule

编译仿真uvm_class_inst.sv，利用UVM类uvm_component来定义顶层class top。

module uvm_class_inst;

  import uvm_pkg::*;
  `include "uvm_macros.svh"

  class top extends uvm_component;
    `uvm_component_utils(top)
    function new(string name = "top", uvm_component parent = null);
      super.new(name, parent);
      `uvm_info("UVM_TOP", "SV TOP creating", UVM_LOW)
    endfunction
  endclass

  initial begin
    top t; 
    `uvm_info("UVM_TOP", "test started", UVM_LOW)
    t = new("t", null);
    `uvm_info("UVM_TOP", "test finished", UVM_LOW)
  end

endmodule

• UVM验证顶层

编译仿真uvm_test_inst.sv

package test_pkg;
  import uvm_pkg::*;
  `include "uvm_macros.svh"

  class top extends uvm_test;
    `uvm_component_utils(top)
    function new(string name = "top", uvm_component parent = null);
      super.new(name, parent);
      `uvm_info("UVM_TOP", "SV TOP creating", UVM_LOW)
    endfunction
    task run_phase(uvm_phase phase);
      phase.raise_objection(this);
      `uvm_info("UVM_TOP", "test is running", UVM_LOW)
      phase.drop_objection(this);
    endtask
  endclass

endpackage

module uvm_test_inst;

  import uvm_pkg::*;
  `include "uvm_macros.svh"
  import test_pkg::*;

  initial begin
    `uvm_info("UVM_TOP", "test started", UVM_LOW)
    run_test("top");
    `uvm_info("UVM_TOP", "test finished", UVM_LOW)
  end

endmodule

只有继承于uvm_test的类，才可以作为UVM验证环境的顶层。

• 开始UVM仿真
  建立顶层验证环境只能通过:

1. 全局函数run_test(“UVM_TEST_NAME”) 指定；
2. 通过仿真传参 +UVM_TESTNAME=<test_name> 指定。

• 结束UVM仿真
  依靠objection机制。

factory的注册、创建和覆盖机制

• UVM只有两种注册宏

`uvm_component_utils(T)
`uvm_object_utils(T)

• 编译仿真factory_mechanism.sv

vsim -novopt -classdebug +UVM_TESTNAME=object_create work.factory_mechanism

  class object_create extends top;
    trans t1, t2, t3, t4;
    `uvm_component_utils(object_create)
    function new(string name = "object_create", uvm_component parent = null);
      super.new(name, parent);
    endfunction    
    function void build_phase(uvm_phase phase);
      uvm_factory f = uvm_factory::get(); // get singleton factory
      super.build_phase(phase);
      t1 = new("t1"); // direct construction
      t2 = trans::type_id::create("t2", this); // common method
      void'($cast(t3,f.create_object_by_type(trans::get_type(), get_full_name(), "t3"))); // factory method
      void'($cast(t4,create_object("trans", "t4"))); // pre-defined method inside component
    endfunction
  endclass

  class object_override extends object_create;
    `uvm_component_utils(object_override)
    function new(string name = "object_override", uvm_component parent = null);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      // 先覆盖后创建
      set_type_override_by_type(trans::get_type(), bad_trans::get_type());
      super.build_phase(phase);
    endfunction
  endclass

  class component_create extends top;
    unit u1, u2, u3, u4;
    `uvm_component_utils(component_create)
    function new(string name = "component_create", uvm_component parent = null);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      uvm_factory f = uvm_factory::get(); // get singleton factory
      super.build_phase(phase);
      u1 = new("u1"); // direct construction
      u2 = unit::type_id::create("u2", this); // common method
      void'($cast(u3,f.create_component_by_type(unit::get_type(), get_full_name(), "u3", this))); // factory method
      void'($cast(u4,create_component("unit", "u4"))); // pre-defined method inside component
    endfunction
  endclass

  class component_override extends component_create;
    `uvm_component_utils(component_override)
    function new(string name = "component_override", uvm_component parent = null);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      set_type_override("unit", "big_unit");
      super.build_phase(phase);
    endfunction
  endclass

field automation机制和uvm_object的常用函数

• field automation机制相关宏

    `uvm_object_utils_begin(trans)
      `uvm_field_int(addr, UVM_ALL_ON)
      `uvm_field_int(data, UVM_ALL_ON)
      `uvm_field_enum(op_t, op, UVM_ALL_ON)
      `uvm_field_string(name, UVM_ALL_ON)
    `uvm_object_utils_end

• copy()函数用于实例复制
• compare()函数用于实例比较
• print()函数用于打印所有字段
• 自定义compare()函数的回调函数do_compare()

    function bit do_compare(uvm_object rhs, uvm_comparer comparer);
      trans t;
      do_compare = 1;
      void'($cast(t, rhs));
      if(addr != t.addr) begin
        do_compare = 0;
        `uvm_warning("CMPERR", $sformatf("addr %8x != %8x", addr, t.addr))
      end
      if(data != t.data) begin
        do_compare = 0;
        `uvm_warning("CMPERR", $sformatf("data %8x != %8x", data, t.data))
      end
      if(op != t.op) begin
        do_compare = 0;
        `uvm_warning("CMPERR", $sformatf("op %s != %8x", op, t.op))
      end
      if(addr != t.addr) begin
        do_compare = 0;
        `uvm_warning("CMPERR", $sformatf("name %8x != %8x", name, t.name))
      end
    endfunction

phase机制

phase机制使得验证环境从组建、连接、执行，得以分阶段执行，按照层次结构和phase顺序严格执行，继而避免一些依赖关系，也使得可以正确地将不同的代码放置到不同的phase块中。

  class phase_order_test extends uvm_test;
    comp1 c1;
    `uvm_component_utils(phase_order_test)
    function new(string name = "phase_order_test", uvm_component parent = null);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      `uvm_info("BUILD", "phase_order_test build phase entered", UVM_LOW)
      c1 = comp1::type_id::create("c1", this);
      `uvm_info("BUILD", "phase_order_test build phase exited", UVM_LOW)
    endfunction
    function void connect_phase(uvm_phase phase);
      super.connect_phase(phase);
      `uvm_info("CONNECT", "phase_order_test connect phase entered", UVM_LOW)
      `uvm_info("CONNECT", "phase_order_test connect phase exited", UVM_LOW)
    endfunction
    task run_phase(uvm_phase phase);
      super.run_phase(phase);
      `uvm_info("RUN", "phase_order_test run phase entered", UVM_LOW)
      phase.raise_objection(this);
      #1us;
      phase.drop_objection(this);
      `uvm_info("RUN", "phase_order_test run phase exited", UVM_LOW)
    endtask
    function void report_phase(uvm_phase phase);
      super.report_phase(phase);
      `uvm_info("REPORT", "phase_order_test report phase entered", UVM_LOW)
      `uvm_info("REPORT", "phase_order_test report phase exited", UVM_LOW)    
    endfunction
    
    task reset_phase(uvm_phase phase);
      `uvm_info("RESET", "phase_order_test reset phase entered", UVM_LOW)
      phase.raise_objection(this);
      #1us;
      phase.drop_objection(this);
      `uvm_info("RESET", "phase_order_test reset phase exited", UVM_LOW)
    endtask
    
    task main_phase(uvm_phase phase);
      `uvm_info("MAIN", "phase_order_test main phase entered", UVM_LOW)
      phase.raise_objection(this);
      #1us;
      phase.drop_objection(this);
      `uvm_info("MAIN", "phase_order_test main phase exited", UVM_LOW)
    endtask 
  endclass

• 除build_phase外所有phase都按照自底向上顺序依次执行。
• run_phase是唯一的task phase，12个细分phase与其并行执行，所以在0时刻，run_phase和reset_phase是并行的，但在shutdown_phase执行完成后，需等run_phase执行完才可进入extract_phase。
• 12个run-time的phase顺序执行（但非立即执行后一个），所以先执行的reset_phase在1000时刻结束，然后main_phase才开始执行，在2000时刻结束。

config机制

set()寄信，get()收信，第一、二个参数组成目标路径，分别是uvm_component对象句柄和相对路径，第三个参数表示传给哪个变量成员，第四个参数是要设置的变量。

• 接口传递

  initial begin
    uvm_config_db#(virtual uvm_config_if)::set(uvm_root::get(), "uvm_test_top.*", "vif", if0);
    run_test("test1"); // 接口传递在run_test()前
  end

• 单一变量传递
• 对象传递

  class config_obj extends uvm_object;
    int comp1_var;
    int comp2_var;
    `uvm_object_utils(config_obj)
    function new(string name = "config_obj");
      super.new(name);
      `uvm_info("CREATE", $sformatf("config_obj type [%s] created", name), UVM_LOW)
    endfunction
  endclass

消息管理

• 使用消息过滤方法set_report_verbosity_level_hier() 在uvm_message_test::build_phase()中屏蔽所有层次的消息，也就是不允许有任何uvm_message_test及其以下组件的消息在仿真时打印出来。

set_report_verbosity_level_hier(UVM_NONE);

• 使用set_report_id_verbosity_level_hier() 来过滤ID的消息，即“Build”、“CREATE”、“RUN”。

uvm_root::get().set_report_id_verbosity_hier("CREATE", UVM_NONE);
uvm_root::get().set_report_id_verbosity_hier("BUILD", UVM_NONE);
uvm_root::get().set_report_id_verbosity_hier("RUN", UVM_NONE);

• 使用消息过滤方法uvm_root::get() 来获取最顶层(即uvm_message_test的顶层)来控制过滤“CREATE”和“TOPTB”的消息。

uvm_root::get().set_report_id_verbosity_hier("TOPTB", UVM_NONE);