数字逻辑设计基础
本文介绍了数字逻辑设计中常用的模块，包括但不限于AND、NAND、OR、NOR等基本逻辑门，以及更复杂的如MUX（多路复用器）、DELAAY（延迟块）、触发器等模块。这些模块在构建复杂的数字系统时扮演着核心角色。
l AND block
l MUX (Multiplexer) block
l ROL (Rotate Output Left) block
l CHECKBAD blockMUXREAL (Real Multiplexer) block
l ROR (Rotate Output Right) block
l DELAY blockMVOTE (Majority Voting) block
l RS (Reset dominant SR-FLIP-FLOP) block
l EQ (Equal) blockNAND block RTRIG (Rising edge Trigger) block
l FTRIG (Falling-edge Trigger) block
l NE (Not Equal) block
l SEL (Binary Selection) block
l GE (Greater than or Equal to) block
l nOON (n out of N voting) block
l SELREAL (Real Selection) block
l GT (Greater Than) block
l NOR blockSHL (Shift Output Left) block
l LE (Less than or Equal to) block
l NOT blockSHR (Shift Output Right) block
l LIMIT blockOFFDELAY block
l SR (Set dominant SR-FLIP-FLOP) block
l LT (Less Than) block
l ONDELAY block
l TRIG (Rising or Falling edge Trigger) block
l MAX block
l OR block
l WATCHDOG block
l MAXPULSE block
l PULSE block
l XOR block
l MIN block
l QOR (Qualified OR) block
l 2OO3 (2 out of 3 voting) block
l MINPULSE block
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