makefile相同目标的合并之问题

 target1: dep1

target1: dep2
           cmd2

这种情况下，这两个相同的target1会被合并成

target1: dep1 dep2          cmd2

但如果第一条规则本身也带一个命令的话， makefile就无法合并， 给出警告，并用后面的规则替代前面的规则

target1: dep1           cmd1 target1: dep2            cmd2

最后生成的是, 其实就是后一条替代了前一条，然后给出警告

 target1: dep2

       cmd2

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makefile中定义一个伪目标，这个伪目标跟.PHONY是不同的，如果一个目标中只是定义一些变量，或者一些调用没有定义相关的command，这就是一个伪目标；

在u-boot的Makefile中有这样的使用：第一个all:用来定义变量和包含相关文件，没有command，  第2个all:有相关规则和command

其实可以这样理解：通过第1个目标(伪目标)进行make前的初始化，第2个目标才是make真正执行的命令

# Include autoconf.mk before config.mk so that the config options are available
# to all top level build files.  We need the dummy all: target to prevent the
# dependency target in autoconf.mk.dep from being the default.
all:
sinclude $(obj)include/autoconf.mk.dep
sinclude $(obj)include/autoconf.mk

# load ARCH, BOARD, and CPU configuration
include $(obj)include/config.mk
export    ARCH CPU BOARD VENDOR SOC

# set default to nothing for native builds
ifeq ($(HOSTARCH),$(ARCH))
CROSS_COMPILE ?= ../buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
endif

# load other configuration
include $(TOPDIR)/config.mk

.....

all:        $(ALL-y)

$(obj)u-boot.hex:    $(obj)u-boot
        $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@

$(obj)u-boot.srec:    $(obj)u-boot
        $(OBJCOPY) -O srec $< $@

$(obj)u-boot.bin:    $(obj)u-boot
        $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
        $(BOARD_SIZE_CHECK)

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 target1:

 CROSS_COMPILE=arm-gcc

target1: dep2
             cmd2

            @echo CROSS_COMPILE is $(CROSS_COMPILE)