ARM base instruction -- negs

Negate, setting flags, negates an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
This instruction is an alias of the SUBS (shifted register) instruction. This means that:

• The encodings in this description are named to match the encodings of SUBS (shifted register).
• The description of SUBS (shifted register) gives the operational pseudocode for this instruction.

取反，设置标志，取一个可选移位的寄存器值的反，并将结果写入目标寄存器。它根据结果更新条件标志。
此指令是SUBS（移位寄存器）指令的别名。这意味着：
•本说明中的编码命名与SUBS（移位寄存器）的编码相匹配。
•SUBS（移位寄存器）的描述给出了此指令的操作伪代码。

32-bit variant
    Applies when sf == 0.
    NEGS <Wd>, <Wm>{, <shift> #<amount>}
    is equivalent to
    SUBS <Wd>, WZR, <Wm> {, <shift> #<amount>}
    and is always the preferred disassembly.

64-bit variant
    Applies when sf == 1.
    NEGS <Xd>, <Xm>{, <shift> #<amount>}
    is equivalent to
    SUBS <Xd>, XZR, <Xm> {, <shift> #<amount>}
    and is always the preferred disassembly.

  415b90:    7100001f     cmp    w0, #0x0
  415b94:    1100fc01     add    w1, w0, #0x3f
  415b98:    1a80b021     csel    w1, w1, w0, lt  // lt = tstop
  415b9c:    6b0003e2     negs    w2, w0
  415ba0:    12001404     and    w4, w0, #0x3f
  415ba4:    12001442     and    w2, w2, #0x3f
  415ba8:    5a824482     csneg    w2, w4, w2, mi  // mi = first