VCS, modelsim, NCsim‘s code coverage

本文详细介绍了在设计和验证复杂系统时如何利用覆盖率来指导验证资源分配,通过识别已测试和未测试的设计部分来减少无效努力。重点讨论了代码覆盖率与功能覆盖率的概念,并提供了在Verilog RTL设计中实现代码覆盖率的技术细节。包括使用VeraSim工具进行代码覆盖率的收集,设置测试脚本以覆盖特定功能,并最终生成HTML报告以分析覆盖率。同时,还介绍了如何在不同验证阶段整合覆盖率数据以获得全面的代码覆盖率视图。

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Coverage

   Functional verification comprises a large portion of the resources required to design and validate a complex system. Often, the validation must be comprehensive without redundant effort. To minimize wasted effort, coverage is used as a guide for directing verification resources by identifying tested and untested portions of the design.

  Coverage is defined as the percentage of verification objectives that have been met. It is used as a metric for evaluating the progress of a verification project in order to reduce the number of simulation cycles spent in verifying a design

There are two types of coverage

1.Code Coverage:Those that can be automatically extracted from the design code(Done by Tool)

2.Functional Coverage:Those that are user-specified in order to tie the verification environment to the design intent or functionality

Code Coverage:

This will give information about how many lines are executed, how many  times expressions, branches executed. This coverage is collected by the  simulation tools.

Let's say,  the specification talks about 3 features, A, B, and C. And let's say  that the RTL designed coded only feature A and B.If the test exercises  only feature A and B, then you can 100% code coverage.From this we cannot say that The design is complete and perfect, because there is one more feature has to be implemented,But the code coverage will not give this information.It gives whether the coded RTL is completely covered or not.For getting the additional information about the specification(features) we have to do the functional coverage.Now we will see how to setup the tool for Code Coverage

Assume that you have already have the RTL ready(Frozen) bye the designers,and the verification plan and test plan also ready,Now you will have different tests to cover feature A,B,and C .Make a regression script in Perl or Shell or any other language, and integrate the following code in the script.

MODELSIM/QUESTA:

//**************************************************************************//

STEP1:Compile your design files with your selected coverage

QuestaSim > vlog +cover bcst -f design_file_list

+cover[=sbceftx]   Enable code coverage metrics by specifying one or

#                      more of the characters:
#                      s statement
#                      b branch
#                      c condition
#                      e expression
#                      f fsm
#                      t toggle
#                      x extended toggle
#                      If no character is specified, sbceft is the default

STEP2:Simulate with the coverage option

QuestaSim > vsim -coverage file_testbench.v

and the run -all

OR, You can enable it using GUI. U go to Compile > Compile Options and select the Coverage tab.Another option, you just right-click on your design file at "Project" and choose "Properties". Now, you can see coverage tab.after running the simulation you will be able to see the coverage tabs for analysis.

If you are running regression you have to save the coverage report of the first test (UCDB file) and merge to the next UCDB of the next test till the regression finishes.And finally you will be able to the  see total Code Coverage.

vsim -c -do "coverage save -onexit <TESTSET_CODE_COVER>.ucdb;run  -all;exit" -coverage -voptargs="+cover=bcfst" <otherOptions>  <TOP>

Here we tell vsim to
1) Enable code coverage (-coverage),
2) The types of coverage to collect (via
-voptargs=+cover= bcefst") if not using the three-step flow process,
3) And to produce a coverage database file on the exit of simulation (do "coverage save -onexit coverage.ucdb)
Continue the step1 and Step2 till the regression ends

STEP3:
Further if you have multiple coverage databases, you can merge them into a single database by using:
vcover merge <ucdbFile1>.ucdb <ucdbFile2>.ucdb ... <ucdbFileN>.ucdb <ucdbFileResult>.ucdb

The finally you can generate a HTML report:
vcover report -html -htmldir <dirToOutput> -verbose -threshL 50 -threshH 90 <ucdbFileResult>.ucdb

NC SIM

//********************************************************************//

ncverilog <OTHER_ARGUMENTS>+nccoverage+all +nccov58 +nccovworkdir+cov_work +nclexpragma +nccovtest+<testcase_name> +nccovoverwrite +nccovdut+worklib.dut_top -T test_top.sv

1. For switching coverage ON:Use +nccovfile+dut_cov.txt while compiling.

//*********************dut_cov.txt****************//
select_coverage -all -module top
.......
select_functional
select_fsm

//************************************************//

During simulation use:
-covoverwrite -covtest mycov.cov


2. To view coverage:
iccr -keywords+detail iccr1.cmd     
OR

iccr -keywords+summary iccr2.cmd OR

iccr -keywords+dontmerge iccr3.cmd


//********************* iccr1.cmd**********************//

merge cov_work/design/test* -output merged_dir

reset_coverage
load_test cov_work/design/merged_dir                                                                     report_detail -instance -betsafd -cgopt top... > detail.rpt

//********************* iccr2.cmd**********************//

merge cov_work/design/test* -output merged_dir
reset_coverage
load_test cov_work/design/merged_dir                                                                report_summary -instance -cgopt top... > summary.rpt

//********************* iccr3.cmd**********************//

load_test cov_work/design/*
report_summary -instance -cgopt top... > summary.rpt

VCS

//********************************************************************//

VSC Coverage report Generation
====================
To generate functional coverage
%urg -dir simv.vdb

To generate code coverage
%vcs -cm_pp -cm_dir simv.cm -cm_name XXX -cm_report summary

Here i am giving you a complete example for coverage with ncverilog, i ll update this later with questa also

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