Conwaylife -- HDLBits Solution
Talk is cheap, show me the code :
module top_module(
input clk,
input load,
input [255:0] data,
output [255:0] q );
reg[3:0] row,col;
reg [2:0] nbs;
always@(posedge clk)begin
if(load)
q<=data;
else begin
for(int i=0;i<256;i++)begin
{row,col}=i;
nbs=
q[{row-4'b1,col-4'b1}]+ q[{row-4'b1,col}]+ q[{row-4'b1,col+4'b1}]+
q[{row ,col-4'b1}]+ q[{row ,col+4'b1}]+
q[{row+4'b1,col-4'b1}]+ q[{row+4'b1,col}]+ q[{row+4'b1,col+4'b1}];
case(nbs)
3:q[i]<=1;
2:q[i]<=q[i];
default:q[i]<=0;
endcase
end
end
end
endmodule