R型+I型+J型指令

fei_sun

于 2024-12-23 16:21:14 发布

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分类专栏：计算机组成原理文章标签：计组

本文链接：https://blog.youkuaiyun.com/wuyufei_sun/article/details/144668354

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23 篇文章

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ori、andi、xori

零扩展

`Inst_ori:
    begin
        op=`Or;
        regaRead=`Valid;
        regbRead=`Invalid;
        regcWrite=`Valid;
        regaAddr=inst[25:21];
        regbAddr=`Zero;
        regcAddr=`inst[20:16];
        imm={16'h0,inst[15:0]};
    end

addi、subi

符号扩展

`Inst_addi:
    begin
        op=`Add;
        regaRead=`Valid;
        regbRead=`Invalid;
        regcWrite=`Valid;
        regaAddr=`inst[25:21];
        regbAddr=`Zero;
        regcAddr=`inst[20:16];
        imm={{16{inst[15]}},inst[15:0]};
    end

lui

`Inst_lui:
    begin
        op=`Lui;
        regaRead=`Invalid;
        regbRead=`Invalid;
        regcWrite=`Valid;
        regaAddr=`Zero;
        regbAddr=`Zero;
        regcAddr=inst[20:16];
        imm={inst[15:0],16'h0};
    end

wire[5:0] func=inst[5:0];

`Inst_r:

case(func)

……

endcase

and、or、xor、add、sub

`Inst_add:
    begin
        op=`Add;
        regaRead=`Valid;
        regbRead=`Valid;
        regcWrite=`Valid;
        regaAddr=inst[25:21];
        regbAddr=inst[20:16];
        regcAddr=inst[15:11]'
        imm=`Zero;
    end

sll、srl、sra

`Inst_sra:
    begin
        op=`Sra;
        regaRead=`Invalid;
        regbRead=`Valid;
        regcWrite=`Valid;
        regaAddr=`Zero;
        regbAddr=inst[20:16];
        regcAddr=inst[15:11];
        imm={27'h0,inst[10:6]};
    end

wire[31:0] npc=pc+4;

rs-->pc

`Inst_jr:
    begin
        op=`Jr;
        regaRead=`Valid;
        regbRead=`Invalid;
        regcWrite=`Invalid;
        regaAddr=inst[25:21];
        regbAddr=`Zero;
        regcAddr=`Zero;
        jAddr=regaData;
        jCe=`Valid;
        imm=`Zero;
    end

jaddr-->pc

`Inst_j:
    begin
        op=`J;
        regaRead=`Invalid;
        regbRead=`Invalid;
        regcWrite=`Invalid;
        regaAddr=`Zero;
        regbAddr=`Zero;
        regcAddr=`Zero;
        jAddr={npc[31:28],inst[25:0],2'b00};
        jCe=`Valid;
        imm=`Zero;
    end

jal

npc-->r31

jaddr-->pc

`Inst_jal:
    begin
        op=`Jal;
        regaRead=`Invalid;
        regbRead=`Invalid;
        regcWrite=`Valid;
        regaAddr=`Zero;
        regbAddr=`Zero;
        regcAddr=5'b11111;
        jAddr={npc[31:28],inst[25:0],2'b00};
        jCe=`Valid;
        imm=npc;
    end

`Inst_beq:
    begin
        op=`Beq;
        regaRead=`Valid;
        regbRead=`Valid;
        regcWrite=`Invalid;
        regaAddr=inst[25:21];
        regbAddr=inst[20:16];
        regcAddr=`Zero;
        jAddr=npc+{{14{inst[15]}},inst[15:0],2'b00};
        jCe=(regaData==regbData)?`Valid:`Invalid;
        imm=`Zero;
    end