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FPGA看图写时序练习1

reg[1:0] cnt_baud; always@(posedge outClk0, negedge SysRst0)begin if(!SysRst0)begin cnt_baud <= 2'b0; end else if(&cnt_baud == 1'd1)begin cnt_baud <= 2'd0; end else begin cnt_baud <= cnt_baud + 1'd1;